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HD74SSTV16859TEL Datasheet(PDF) 1 Page - Renesas Technology Corp |
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HD74SSTV16859TEL Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 11 page Rev.9.00 Apr 07, 2006 page 1 of 10 HD74SSTV16859 1:2 13-bit SSTL_2 Registered Buffer REJ03D0832-0900 (Previous: ADE-205-337H) Rev.9.00 Apr 07, 2006 Description The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset ( RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to QA, QB is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock ( CLK) must be used to maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. Features • Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input • Differential SSTL_2 (Stub series terminated logic) CLK signal • Flow through architecture optimizes PCB layout • Ordering Information Part Name Package Type Package Code (Previous code) Package Abbreviation Taping Abbreviation (Quantity) HD74SSTV16859TEL TSSOP-64 pin PTSP0064KA-A (TTP-64DV) T EL (1,000 pcs / Reel) Function Table Inputs Outputs RESET CLK CLK D QA QB L X X X L L H ↓ ↑ H H H H ↓ ↑ L L L H L or H H or L X Q0 *1 Q0 *1 H : High level L : Low level X : Immaterial ↑ : Low to high transition ↓ : High to low transition Note: 1. Output level before the indicated steady state input conditions were established. |
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