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R1Q4A3618BBG-33R Datasheet(PDF) 1 Page - Renesas Technology Corp |
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R1Q4A3618BBG-33R Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 26 page REJ03C0343-0003 Rev.0.03 Apr.11,2008 Page 1 of 24 R1Q4A3636B/R1Q4A3618B 36-Mbit DDRII SRAM 2-word Burst REJ03C0343-0003 Preliminary Rev. 0.03 Apr.11, 2008 Description The R1Q4A3636B is a 1,048,576-word by 36-bit, the R1Q4A3618B is a 2,097,152-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package. Features • 1.8 V ± 0.1 V power supply for core (V DD) • 1.4 V to V DD power supply for I/O (VDDQ) • DLL circuitry for wide output data valid window and future frequency scaling • Pipelined double data rate operation • Common data input/output bus • Two-tick burst for low DDR transaction size • Two input clocks (K and /K) for precise DDR timing at clock rising edges only • Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop capability with µs restart • User programmable impedance output • Fast clock cycle time: 3.3 ns (300 MHz)/4.0 ns (250 MHz)/ 5.0 ns (200 MHz)/6.0 ns (167 MHz) • Simple control logic for easy depth expansion • JTAG boundary scan Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology's Sales Dept. regarding specifications. |
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