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R1Q5A3636BBG-40R Datasheet(PDF) 9 Page - Renesas Technology Corp |
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R1Q5A3636BBG-40R Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 25 page R1Q5A3636B/R1Q5A3618B REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 9 of 23 Byte Write Truth Table (x18) Operation K /K /BW0 /BW1 Write D0 to D17 ↑ L L ↑ L L Write D0 to D8 ↑ L H ↑ L H Write D9 to D17 ↑ H L ↑ H L Write nothing ↑ H H ↑ H H Notes: 1. H: high level, L: low level, ↑: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Bus Cycle State Diagram NOP Write Double Count = Count + 2 Load New Address Count = 0 Power Up /LD = H Supply voltage provided /LD = L R-/W = L /LD = L & Count = 4 Advance Address by Two Always Count = 2 /LD = H & Count = 4 Read Double Count = Count + 2 R-/W = H /LD = L & Count = 4 Advance Address by Two Always Count = 2 /LD = H & Count = 4 Notes: 1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated at the end of this sequence (burst count = 4). 2. State machine control timing sequence is controlled by K. |
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