R1Q5A3636B/R1Q5A3618B

REJ03C0344-0003 Rev.0.03 Apr.11, 2008

page 6 of 23

General Description

Power-up and Initialization Sequence

After the stable power, there are three possible sequences.

1. Sequence when DLL disable (/DOFF pin fixed low)

Just after the stable power and clock (K, /K, C, /C), 1024 NOP cycles (min.) are required for all operations,

including JTAG functions, to become normal.

2a. Sequence controlled by /DOFF pin when DLL enable Just after the stable power and clock (K, /K, C, /C), take

/DOFF to be high.

The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal.

2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable If /DOFF pin is fixed high with

unstable clock, the clock (K, /K, C, /C) must be stopped for 30ns (min.).

The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal.

Notes: 1. After K or C clock is stopped, clock recovery cycles (1024 NOP cycles (min.)) are required for read/write

operations to become normal.

2. When DLL is enable and the operating frequency is changed, DLL reset should be required again. After DLL

reset again, the 1024 NOP cycles (min.) are needed to lock the DLL.

1. Sequence when DLL disable (/DOFF pin fixed low)

Status

Power Up

Unstable

Clock Stage

Stable

Clock Stage

NOP Stage

Normal

Operation

K, /K

C, /C,

1024cycle min.

2a. Sequence controlled by /DOFF pin when DLL enable

Status

Power Up

Unstable

Clock Stage

Stable

Clock Stage

NOP & DLL

Locking Stage

Normal

Operation

K, /K

C, /C,

1024cycle min.

/DOFF