 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
R8A66161DD Datasheet(PDF) 2 Page - Renesas Technology Corp |
|
||||||||||||||||||||||||||||||
R8A66161DD Datasheet(HTML) 2 Page - Renesas Technology Corp |
|
|
2 / 8 page  R8A66161DD/SP REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 2 of 7 PIN CONFIGURATION ( TOP VIEW ) FUNCTIONAL DESCRIPTION As R8A66161 uses silicon gate CMOS process. It realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shift register consists of two flip-flop having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when “L” changes to “H”. Serial data input A is the data input of the first-step shift register and the signal of A shifts shifting registers one by one when a pulse is impressed to CKS. When A is “H”, the signal of “L” shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the parallel data outputs from QA ~ QP. Outputs QA ~ QP are open drain outputs. To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th bit. When reset input R is changed to “L”, QA ~ QP and SQP are reset. In this case, shifting and latching register are set. If “H” is impressed to output enable input OE, QA ~ QP reaches the high impedance state, but SQP does not reach the high impedance state. Furthermore, change in OE does not affect shift operation. FUNCTION TABLE (Note: 1) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 QA QB A OE CKL R CKS SQP QO QP QC QD QE QF QG QH QI QJ QK QL QM QN A CKL CKS SQP QC QD QE QF QG QH QI QJ QK QL QM QN PARALLEL DATA OUTPUTS SERIAL DATA INPUT ENABLE INPUT LATCH CLOCK INPUT DIRECT RESET INPUT SHIFT CLOCK INPUT SERIAL DATA OUTPUT PARALLEL DATA OUTPUTS PARALLEL DATA OUTPUTS VCC GND QA QB OE R QO QP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 QA QB A OE CKL R CKS SQP QO QP QC QD QE QF QG QH QI QJ QK QL QM QN A CKL CKS SQP QC QD QE QF QG QH QI QJ QK QL QM QN PARALLEL DATA OUTPUTS SERIAL DATA INPUT ENABLE INPUT LATCH CLOCK INPUT DIRECT RESET INPUT SHIFT CLOCK INPUT SERIAL DATA OUTPUT PARALLEL DATA OUTPUTS PARALLEL DATA OUTPUTS VCC GND QA QA QB QB OE OE R R QO QO QP QP : Change from low-level to high-level : Output state Q before CKL changed : Irrelevant : Contents of shift register before CKS changed : Contents of shift register : t2 is set after t1 is set : High impedance Note1: ↑ Q X q q t1, t2 Z 0 0 Operation mode Shift Latch operation Input Parallel data output CKS CKL A R OE QA QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP Serial data output SQP Remarks Shift t1 H ↑ XH L QA 0 QB 0 QC 0 QD 0 QE 0 QF 0 QG 0 QH 0 QI 0 QJ 0 QK 0 QL 0 QM 0 QN 0 QO 0 QP 0 qO0 Latch t2 HX ↑ XL L qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL0 qM0 qN0 qO0 qO0 Shift t1 H ↑ XL L QA 0 QB 0 QC 0 QD 0 QE 0 QF 0 QG 0 QH 0 QI 0 QJ 0 QK 0 QL 0 QM 0 QN 0 QO 0 QP 0 qO0 Latch t2 HX ↑ XL Z qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL0 qM0 qN0 qO0 qO0 Reset LX X X X Z Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z L Output Lighting H Output disable X X X X H Z ZZ Z Z Z Z Z Z Z Z ZZ Z Z Z qP Output Lights-out L : Change from low-level to high-level : Output state Q before CKL changed : Irrelevant : Contents of shift register before CKS changed : Contents of shift register : t2 is set after t1 is set : High impedance Note1: ↑ Q X q q t1, t2 Z 0 0 : Change from low-level to high-level : Output state Q before CKL changed : Irrelevant : Contents of shift register before CKS changed : Contents of shift register : t2 is set after t1 is set : High impedance Note1: ↑ Q X q q t1, t2 Z 0 0 Operation mode Shift Latch operation Input Parallel data output CKS CKL A R OE QA QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP Serial data output SQP Remarks Shift t1 H ↑ XH L QA 0 QB 0 QC 0 QD 0 QE 0 QF 0 QG 0 QH 0 QI 0 QJ 0 QK 0 QL 0 QM 0 QN 0 QO 0 QP 0 qO0 Latch t2 HX ↑ XL L qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL0 qM0 qN0 qO0 qO0 Shift t1 H ↑ XL L QA 0 QB 0 QC 0 QD 0 QE 0 QF 0 QG 0 QH 0 QI 0 QJ 0 QK 0 QL 0 QM 0 QN 0 QO 0 QP 0 qO0 Latch t2 HX ↑ XL Z qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL0 qM0 qN0 qO0 qO0 Reset LX X X X Z Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z L Output Lighting H Output disable X X X X H Z ZZ Z Z Z Z Z Z Z Z ZZ Z Z Z qP Output Lights-out L Operation mode Shift Latch operation Input Parallel data output CKS CKL A R OE QA QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP Serial data output SQP Remarks Shift t1 H ↑ XH L QA 0 QB 0 QC 0 QD 0 QE 0 QF 0 QG 0 QH 0 QI 0 QJ 0 QK 0 QL 0 QM 0 QN 0 QO 0 QP 0 qO0 Latch t2 HX ↑ XL L qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL0 qM0 qN0 qO0 qO0 Shift t1 H ↑ XL L QA 0 QB 0 QC 0 QD 0 QE 0 QF 0 QG 0 QH 0 QI 0 QJ 0 QK 0 QL 0 QM 0 QN 0 QO 0 QP 0 qO0 Latch t2 HX ↑ XL Z qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL0 qM0 qN0 qO0 qO0 Reset LX X X X Z Z Z Z Z Z Z Z Z ZZ Z Z Z Z Z L Output Lighting H Output disable X X X X H Z ZZ Z Z Z Z Z Z Z Z ZZ Z Z Z qP Output Lights-out L |
Similar Part No. - R8A66161DD |
|
Similar Description - R8A66161DD |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
