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M3826AE3FS Datasheet(PDF) 8 Page - Renesas Technology Corp

Part # M3826AE3FS
Description  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M3826AE3FS Datasheet(HTML) 8 Page - Renesas Technology Corp

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Rev.1.00
Sep 06, 2006
page 8 of 88
REJ03B0181-0100
3826 Group (One Time PROM version)
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3826 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The central processing unit (CPU) has six registers. Figure 6
shows the 740 Family CPU register structure.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as
arithmetic data transfer, etc., are executed mainly through the ac-
cumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Figure 7 shows the operations of pushing register contents onto
the stack and popping them from the stack. Table 4 shows the
push and pop instructions of accumulator or processor status reg-
ister.
Store registers other than those described in Figure 7 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 6 740 Family CPU register structure
AAccumulator
b7
b7
b7
b7
b0
b7
b15
b0
b7
b0
b0
b0
b0
X
Index register X
Y
Index register Y
SStack pointer
PCL
Program counter
PCH
N VTB DI ZC
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag


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