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R1Q4A3609ABG60RS0 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R1Q4A3609ABG60RS0 Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 26 page R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 11 of 24 Bus Cycle State Diagram Read Port NOP RInit = 0 Read Double Load New Read Address Power Up /R = H Write Port NOP /W = H Supply voltage provided Supply voltage provided /R = L Always /R = L /R = H Write Double at /K ↑ Load New Write Address at /K ↑ /W = L Always /W = L /W = H Notes: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as: xxx…xxx+0, xxx…xxx+1. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. Read and write state machines can be active simultaneously. 3. State machine control timing sequence is controlled by K. |
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