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M66282FP Datasheet(PDF) 9 Page - Renesas Technology Corp |
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M66282FP Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 14 page M66282FP REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 9 of 13 Variable Length Delay Bit 1 Line (8192 Bits) Delay Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay. WCK RCK Dn Qn WRESB RRESB (8189) (8190) (8191) (2) (1) (0) WEB, REB = "L" (0') (1') (2') (3') tRESH tRESS tDH tDS tDH tOH tAC 8192 cycle tDS 1 cycle 0 cycle 8190 cycle 8191 cycle 8192 cycle (0') 8193 cycle (1') 8194 cycle (2') 2 cycle (0) (1) (2) (3) n-bit Delay Bit (Reset at cycles according to the delay length) WCK RCK Dn Qn WRESB RRESB (n − 3) (n − 2) (n − 1) (2) (1) (0) WEB, REB = "L" (0') (1') (2') (3') tRESH tRESS tDH tDS tDH tOH tAC m cycle tDS tRESH tRESS 1 cycle 0 cycle n − 2 cycle n − 1 cycle n cycle (0') n + 1 cycle (1') n + 2 cycle (2') n + 3 cycle (3') 2 cycle (0) (1) (2) (3) |
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