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M62333P Datasheet(PDF) 6 Page - Renesas Technology Corp |
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M62333P Datasheet(HTML) 6 Page - Renesas Technology Corp |
6 / 10 page M62333P/FP, M62338P/FP REJ03D0865-0400 Rev.4.00 Mar 25, 2008 Page 6 of 9 Timing Chart (Model) 12345678 A SDA SCL D/A output SDA SCL D/A output 1234567 1234567 W A SDA SCL 8 A D/A output <Start condition to slave address bit> <Sub address bit> <DAC data bit to stop condition> Start condition Stop condition • Start condition With SCL at High, SDA line goes from High to Low • Stop condition With SCL at High, SDA line goes from Low to High (Under normal circumstances, SDA is changed when SCL is Low) • Acknowledge bit The receiving IC has to pull down SDA line whenever receive slave data. (The transmitting IC releases the SDA line just then transmit 8-bit data.) Digital Data Formats STA Slave address W A Sub address 2 A DAC data 2 A STP Sub address 1 A DAC data 1 A Sub address n A DAC data n A ………… |
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