HM64YLB36512 Series

Rev.3.00 Jan 13, 2006 page 5 of 29

Pin Descriptions

Name

I/O type

Descriptions

Notes

Supply

Core power supply

Supply

Ground

Supply

Output power supply

Supply

Input reference, provides input reference voltage

K

Input

Clock input, active high

K

Input

Clock input, active low

SS

Input

Synchronous chip select

SWE

Input

Synchronous write enable

SAn

Input

Synchronous address input

n: 1 to 18

(Late select mode)

(Late write mode)

n: 0 to 18

(Register-latch mode)

SAS

Input

Late select: Synchronous way select

Late write: Synchronous address input

SA0 in the register-latch

mode

SWEx

Input

Synchronous byte write enables

x: a to d

G

Input

Asynchronous output enable

ZZ

Input

Power down mode select

ZQ

Input

Output impedance control

1

DQxn

I/O

Synchronous data input/output

x: a to d

n: 0 to 8

M1, M2

Input

Output protocol mode select

TMS

Input

Boundary scan test mode select

TCK

Input

Boundary scan test clock

TDI

Input

Boundary scan test data input

TDO

Output

Boundary scan test data output

NC



No connection

M1

M2

Protocol

Notes

Synchronous register to register operation (late select mode)

2

Synchronous register to register operation (late write mode)

3

Synchronous register to latch operation (register-latch mode)

2

buffer impedance will be maximum.

2. Mode control pins M1 and M2 are used to select different read protocols.

These mode control input pins are set at power-up and will not change the states during the SRAM operates.

Late select mode: Single clock, late SAS select, pipelined read protocol

Late write mode: Single clock, pipelined read protocol

Register-latch mode: Single differential clock register-latch mode protocol