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HD404054S Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # HD404054S
Description  microcomputer designed to increase program productivity
Download  103 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD404054S Datasheet(HTML) 9 Page - Renesas Technology Corp

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HD404054 Series/HD404094 Series
7
0
$000
$000
64
80
576
960
1023
$040
$050
4
5
6
7
0
3
12
13
14
15
8
9
11
16
17
32
35
18
19
20
63
$003
$004
$005
$006
$007
$008
$009
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$020
$023
$032
$033
$034
$035
$03F
$00E
$00F
W
W
R/W
W
W
W
W
W
W
W
W
W
W
W
R
R
W
R/W
R/W
R/W
$3C0
$240
RAM-mapped registers
Memory registers (MR)
Data (432 digits)
Stack (64 digits)
Interrupt control bits area
Port mode register A
Serial mode register 1A
Serial data register 1 lower
Serial data register 1 upper
Timer mode register A
Miscellaneous register
Timer mode register C1
Timer C
Timer mode register D2
Register flag area
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port D to D DCR
Port D to D DCR
Port D and D DCR
0
3
47
89
14
15
Timer read register C lower
Timer read register C upper
Timer write register C lower
Timer write register C upper
$090
R:
W:
R/W:
Read only
Write only
Read/Write
$011
$012
W
W
R
R
17
18
Timer read register D lower
Timer read register D upper
Timer write register D lower
Timer write register D upper
144
W
Timer mode register D1
R/W
R/W
Timer D
Timer mode register C2
21
$015
22
$016
R
Compare data register
23
$017
36
$024
37
$025
38
$026
39
$027
40
$028
41
$029
42
$02A
43
$02B
24
25
31
$018
$019
$01F
$3FF
Compare enable register
W
W
W
44
45
46
47
Port mode register B
Port mode register C
Detection edge select register 2
Serial mode register 1B
Port R4 DCR
W
W
W
$02C
$02D
$02E
$02F
$031
$030
53
48
49
50
51
52
Two registers are mapped
on the same area.
R/W
R/W
(PMRA)
(SM1A)
(SR1L)
(SR1U)
(TMA)
(MIS)
(TMC1)
(TRCL/TWCL)
(TRCU/TWCU)
(TMD1)
(TRDL/TWDL)
(TRDU/TWDU)
(TMC2)
(TMD2)
(CDR)
(CER)
(PMRB)
(PMRC)
(SM1B)
(ESR2)
(DCD0)
(DCD1)
(DCD2)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(TRCL)
(TRCU)
(TRDL)
(TRDU)
(TWCL)
(TWCU)
(TWDL)
(TWDU)
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Figure 2 RAM Memory Map


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