HD404326US datasheet(8/103 Pages) RENESAS

Part #	HD404326US

Description	microcomputer designed to increase program productivity

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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HD404054 Series/HD404094 Series

6

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses

of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the

vector address.

Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a

subroutine in this area in response to the CAL instruction.

Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000–$07FF (HD404052, HD40A4052, HD404092), $0000–$0FFF (HD404054,

HD40A4054, HD4074054, HD404094, HD4074094)): Used for program coding.

0

15

16

63

64

2047

0

$000F

$07FF

$003F

$0040

Vector address

Zero-page subroutine

(64 words)

Program & Pattern

2048 words

(HD404052, HD40A4052,

HD404092)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

$0000

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

0

1

JMPL instruction

(Jump to

RESET, STOPC routine)

JMPL instruction

(Jump to

INT routine)

JMPL instruction

(Jump to timer A routine)

JMPL instruction

(Jump to timer D, routine)

JMPL instruction

(Jump to

INT routine)

JMPL instruction

(Jump to serial 1 routine)

JMPL instruction

(Jump to timer C, routine)

Not used

$0010

4096 words

(HD404054, HD40A4054,

HD4074054,HD404094,

HD4074094)

4095

$0FFF

Figure 1 ROM Memory Map

RAM Memory Map

The MCU contains a 512-digit

× 4-bit RAM area consisting of a memory register area, a data area, and a

stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped

onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM

memory map is shown in figure 2 and described as follows.

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