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4507 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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4507 Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 115 page 4507 Group Rev.3.01 2005.02.04 page 9 of 111 REJ03B0107-0301 Port block diagram (3) P10, P11 (Note 3) Register A Ai Ai D TQ (Note 2) K1i PU1i (Note 2) (Note 2) A3 A3 D T Q PU13 P13/INT (Note 3) K13 K13 P12/CNTR (Note 3) A2 A2 D TQ K12 PU12 W60 0 1 W20 W21 IAP1 instruction OP1A instruction (Note 1) “L” level detection circuit This symbol represents a parasitic diode on the port. 2: i represents 0 or 1. 3: Applied potential to port P1 must be VDD or less. Notes 1: Key-on wakeup input Pull-up transistor Register A IAP1 instruction OP1A instruction (Note 1) “L” level detection circuit Key-on wakeup input Pull-up transistor Clock input for timer 2 event counter Timer 1 or timer 2 underflow signal divided by 2 “L” level detection circuit Key-on wakeup input Pull-up transistor Register A IAP1 instruction OP1A instruction External 0 interruptExternal interrupt circuit (Note 1) |
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