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4519 Datasheet(PDF) 7 Page - Renesas Technology Corp

Part # 4519
Description  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4519 Datasheet(HTML) 7 Page - Renesas Technology Corp

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4519 Group
Rev.3.01
2005.06.15
page 7 of 160
REJ03B0007-0301
CONNECTIONS OF UNUSED PINS
Connection
Open.
Open.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
Pin
XIN
XOUT
D0–D5
D6/CNTR0
D7/CNTR1
P00–P03
P10–P13
P20/SCK
P21/SOUT
P22/SIN
P30/INT0
P31/INT1
P32, P33
P40/AIN4–P43/AIN7
P50–P53
P60/AIN0–P63/AIN3
Usage condition
Internal oscillator is selected.
(Note 1)
Internal oscillator is selected.
(Note 1)
RC oscillator is selected.
(Note 2)
External clock input is selected for main clock.
(Note 3)
N-channel open-drain is selected for the output structure.
(Note 4)
CNTR0 input is not selected for timer 1 count source.
N-channel open-drain is selected for the output structure.
(Note 4)
CNTR1 input is not selected for timer 3 count source.
N-channel open-drain is selected for the output structure.
(Note 4)
The key-on wakeup function is not selected.
(Note 6)
N-channel open-drain is selected for the output structure.
(Note 5)
The pull-up function is not selected.
(Note 4)
The key-on wakeup function is not selected.
(Note 6)
The key-on wakeup function is not selected.
(Note 7)
N-channel open-drain is selected for the output structure.
(Note 5)
The pull-up function is not selected.
(Note 4)
The key-on wakeup function is not selected.
(Note 7)
SCK pin is not selected.
SIN pin is not selected.
“0” is set to output latch.
“0” is set to output latch.
N-channel open-drain is selected for the output structure.
Notes 1: After system is released from reset, the internal oscillation (on-chip oscillator) is selected for system clock (RG0=0, MR0=1).
2: When the CRCK instruction is executed, the RC oscillation circuit becomes valid. Be careful that the swich of system clock is not executed at oscilla-
tion start only by the CRCK instruction execution.
In order to start oscillation, setting the main clock f(XIN) oscillation to be valid (MR1=0) is required. (If necessary, generate the oscillation stabilizing
wait time by software.)
Also, when the main clock (f(XIN)) is selected as system clock, set the main clock f(XIN) oscillation (MR1=0) to be valid, and select main clock f(XIN)
(MR0=0). Be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started.
3: In order to use the external clock input for the main clock, select the ceramic resonance by executing the CMCK instruction at the beggining of soft-
ware, and then set the main clock (f(XIN)) oscillation to be valid (MR1=0). Until the main clock (f(XIN)) oscillation becomes valid (MR1=0) after ceramic
resonance becomes valid, XIN pin is fixed to “H”. When an external clock is used, insert a 1 k
Ω resistor to XIN pin in series for limits of current.
4: Be sure to select the output structure of ports D0–D5 and the pull-up function of P00–P03 and P10–P13 with every one port. Set the corresponding
bits of registers for each port.
5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one
open.
6: The key-on wakeup function is selected with every two bits. When only one of key-on wakeup function is used, considering that the value of key-on
wake-up control register K1, set the unused 1-bit to “H” input (turn pull-up transistor ON and open) or “L” input (connect to VSS, or open and set the
output latch to “0”).
7: The key-on wakeup function is selected with every two bits. When one of key-on wakeup function is used, turn pull-up transistor of unused one ON
and open.
(Note when connecting to VSS and VDD)
q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.


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