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M34518E8SP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M34518E8SP Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 160 page Rev.3.01 2005.06.15 page 11 of 157 REJ03B0008-0301 4518 Group Port block diagram (3) P00, P01 OP0A instruction Register A Aj Aj D (Note 2) (Note 1) FR00 IAP0 instruction PU0j Pull-up transistor TQ This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. Notes 1: (Note 1) K00 Key-on wakeup Level detection circuit Edge detection circuit 0 1 K11 0 1 K10 (Note 3) P02, P03 OP0A instruction Register A Ak Ak D (Note 2) (Note 1) FR01 IAP0 instruction PU0k Pull-up transistor TQ (Note 1) K01 Key-on wakeup Level detection circuit Edge detection circuit 0 1 K13 0 1 K12 (Note 4) P10, P11 OP1A instruction Register A Aj Aj D (Note 2) (Note 1) FR02 IAP1 instruction PU1j Pull-up transistor TQ (Note 1) K02 (Note 3) P12, P13 OP1A instruction Register A Ak Ak D (Note 2) (Note 1) FR03 IAP1 instruction PU1k Pull-up transistor TQ (Note 1) K03 Key-on wakeup Level detection circuit (Note 4) (Note 3) (Note 4) (Note 3) (Note 4) Key-on wakeup Level detection circuit |
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