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M34552MXH-XXXFP Datasheet(PDF) 6 Page - Renesas Technology Corp |
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M34552MXH-XXXFP Datasheet(HTML) 6 Page - Renesas Technology Corp |
6 / 145 page Rev.3.02 Dec 22, 2006 page 6 of 142 REJ03B0023-0302 4552 Group DEFINITION OF CLOCK AND CYCLE q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. • Clock (f(XIN)) by the external ceramic resonator • Clock (f(XIN)) by the external RC oscillation • Clock (f(XIN)) by the external input • Clock (f(RING)) of the on-chip oscillator which is the internal oscillator • Clock (f(XCIN)) by the external quartz-crystal resonator Register MR System clock f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) Table Selection of system clock Note: The f(RING)/8 is selected after system is released from reset. MR2 1 0 1 0 1 0 1 0 1 0 1 0 MR3 1 1 0 0 1 1 0 0 1 1 0 0 Operation mode Internal frequency divided by 8 mode Internal frequency divided by 4 mode Internal frequency divided by 2 mode Internal frequency through mode High-speed frequency divided by 8 mode High-speed frequency divided by 4 mode High-speed frequency divided by 2 mode High-speed through mode Low-speed frequency divided by 8 mode Low-speed frequency divided by 4 mode Low-speed frequency divided by 2 mode Low-speed through mode q System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. q Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle gen- erates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction. MR0 0 0 0 0 1 1 1 1 0 0 0 0 MR1 0 0 0 0 0 0 0 0 1 1 1 1 PORT FUNCTION Port Port D Port P0 Port P1 Port P2 Port C I/O unit 1 4 4 4 1 Control instructions SD, RD SZD CLD OP0A IAP0 OP1A IAP1 OP2A IAP2 RCP SCP Control registers FR1, FR2 I1, K2 RG FR0, PU0 K0 C1 FR0, PU1 K0, K1 C2 FR2 L3 W1 Output structure N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain/ CMOS CMOS Input Output I/O (6) Output (2) I/O (4) I/O (4) I/O (4) Output (1) Remark Pin D0–D4, D5/INT XCIN/D6, XCOUT/D7 P00/SEG21–P03/SEG24 P10/SEG25–P13/SEG28 P20/SEG17–P23/SEG20 C/CNTR Output structure selection function (programmable) Built-in pull-up functions, key-on wakeup functions and output structure selection function (programmable) Built-in pull-up functions, key-on wakeup functions and output structure selection function (programmable) Output structure selection func tion (programmable) |
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