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M37545G1KP Datasheet(PDF) 10 Page - Renesas Technology Corp |
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M37545G1KP Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 62 page Rev.1.06 Mar 07, 2008 Page 10 of 59 REJ03B0140-0106 7545 Group Fig. 8 Register push and pop at interrupt generation and subroutine call Execute JSR On-going Routine M (S) (PCH) M (S) (PCL) Execute RTS (PCL) M (S) (S) (S + 1) (S) (S + 1) (PCH) M (S) Subroutine Restore Return Address Store Return Address on Stack M (S) (PS) Execute RTI (PS) M (S) Interrupt Service Routine Restore Contents of Processor Status Register M (S) (PCH) (S) (S - 1) M (S) (PCL) (PCL) M (S) (PCH) M (S) Restore Return Address I Flag “0” to “1” Fetch the Jump Vector Store Return Address on Stack Store Contents of Processor Status Register on Stack Interrupt request (Note) Note : The condition to enable the interrupt Interrupt enable bit is “1” Interrupt disable flag is “0” (S) (S - 1) (S) (S - 1) (S) (S + 1) (S) (S + 1) (S) (S + 1) (S) (S - 1) (S) (S - 1) Table 5 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP |
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