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M37545G4GP Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # M37545G4GP
Description  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M37545G4GP Datasheet(HTML) 3 Page - Renesas Technology Corp

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Rev.1.06
Mar 07, 2008
Page 3 of 59
REJ03B0140-0106
7545 Group
Table 1
Performance overview (1)
Parameter
Function
Number of basic instructions
71
Instruction execution time
2.00
µs (Minimum instruction)
Memory sizes
ROM
M37545G1
4096 bytes
× 8 bits
M37545G2
8192 bytes
× 8 bits
M37545G4
16384 bytes
× 8 bits
M37545G6
24576 bytes
× 8 bits
M37545G8
32768 bytes
× 8 bits
M37545GC
49152 bytes
× 8 bits
M37545GF
61440 bytes
× 8 bits
RAM
M37545G1/G2
RAM1: 240 bytes
× 8 bits, RAM2: 16 bytes × 8 bits
M37545G4/G6/G8/GC/GF
RAM1: 384 bytes
× 8 bits, RAM2: 128 bytes × 8 bits
I/O port
P00
−P07
I/O
• 1-bit
× 8
• CMOS compatible input level
• CMOS 3-state output structure
• Whether the pull-up function/key-on wakeup function is to be used or not
can be determined by program.
P10, P11
I/O (RLSS-only pin)
• 1-bit
× 2
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
P20
−P27
I/O
• 1-bit
× 8
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
• P2 can output a large current for driving LED.
•P20 and P21 are also used as INT0 and INT1, respectively.
P30
−P37
I/O
• 1-bit
× 8
• CMOS compatible input level
• The output structure can be switched to N-channel open-drain or CMOS by software.
P40, P41
I/O (RLSS-only pin)
• 1-bit
× 2
• CMOS compatible input level
• CMOS 3-state output structure
P42
I/O
• 1-bit
× 1
• CMOS compatible input level
• CMOS 3-state output structure
• Carrier wave output pin for remote-control transmitter
Timer
Timer 1
8-bit timer with timer 1 latch
Count source is Prescaler output.
Timer 2
8-bit timer with timer 2 primary latch and timer 2 secondary latch
Count source can be selected from f(XIN)/16, f(XIN)/8, f(XIN)/2 or f(XIN)/1.
Timer 3
8-bit timer with timer 3 latch
Count source can be selected from f(XIN)/16, f(XIN)/8 or f(XIN)/2 or carrier wave output.
Carrier wave generating circuit
Remote-control waveform is generated by using timer 2 and timer 3.
455 kHz carrier wave generating mode is available.
Watchdog timer
16-bit
× 1
Power-on reset circuit
Built-in
Voltage drop detection circuit (Not available for RLSS)
Typ. 1.75 V (Ta=25
°C)
Interrupt
Source
7 sources (External
× 3, Timer × 3, Software)
Function set
ROM area
Function set ROM
Function set ROM is assigned to address FFDA16.
Enable/disable of watchdog timer and STP instruction can be selected.
Valid/invaid of voltage drop detection circuit can be selected.
ROM code protect
ROM code protect is assigned to address FFDB16.
Read/write the built-in QzROM by serial programmer is disabled by setting
00to ROM code protect.
Device structure
CMOS silicon gate
Package
32-pin plastic molded LQFP (PLQP0032GB-A)
32-pin plastic molded SSOP (PLSP0032JB-A)
Operating temperature range
−20 to 85 °C
Power source
voltage
f(XIN) = 4 MHz
1.8 to 3.6 V


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