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M37754M6C-XXXGP Datasheet(PDF) 8 Page - Renesas Technology Corp |
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M37754M6C-XXXGP Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 14 page 7 MITSUBISHI MICROCOMPUTERS M37754M6C-XXXGP M37754M6C-XXXHP PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS The M37754M6C-XXXGP and M37754M6C-XXXHP has the same functions as the M37754M8C-XXXGP and M37754M8C-XXXHP ex- cept for the following : (1) The ROM size is different. (2) The function of ROM area modification is not available. Therefore, refer to the section on the M37754M8C-XXXGP. MEMORY The memory map is shown in Figure 1. The address space is 16 Mbytes from addresses 016 to FFFFFF16. The address space is di- vided into 64-Kbyte units called banks. The banks are numbered from 016 to FF16. Internal ROM, internal RAM, and control registers for internal periph- eral devices are assigned to bank 016. The 48-Kbyte area from addresses 400016 to FFFF16 is the internal ROM. Addresses FFD216 to FFFF16 are the RESET and interrupt vector addresses and contain the interrupt vectors. Refer to the section on interrupts for details. The 2048-byte area from addresses 8016 to 87F16 contains the inter- nal RAM. In addition to storing data, the RAM is used as stack during a subroutine call, or interrupts. Assigned to addresses 016 to 7F16 are peripheral devices such as I/O ports, A-D converter, D-A converter, UART, timer, and interrupt control registers. A 256-byte direct page area can be allocated anywhere in bank 016 using the direct page register DPR. In direct page addressing mode, the memory in the direct page area can be accessed with two words thus reducing program steps. Note: Internal ROM area can be modified. (Refer to the section on ROM area modification function.) 00000016 00000016 00000016 00007F16 00087F16 00FFFF16 00FFFE16 00FFD216 00008016 00FFFF16 Bank 016 Bank 116 01000016 01FFFF16 FF000016 FFFFFF16 Internal RAM 2048 bytes Peripherai devices control registers Interrupt vector table A-D INT3 UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 Watchdog timer BRK instruction Zero divide see Fig. 2 for further information INT1 INT0 DBC RESET Bank FF16 • • • • • • • • • • • • • Internal ROM 48 Kbytes 00400016 FE000016 FEFFFF16 Bank FE16 00007F16 INT4 Fig. 1 Memory map |
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