MITSUBISHI LSIs

M5M5V5A36GP-75,85

18874368-BIT(524288-WORD BY 36-BIT)

Flow-Through NETWORK SRAM

7/19

Preliminary

M5M5V5A36GP REV.0.1

DC OPERATED TRUTH TABLE

Name

Input Status

Operation

HIGH or NC

Interleaved Burst Sequence

LBO#

LOW

Linear Burst Sequence

Note4. LBO# is DC operated pin.

Note5. NC means No Connection.

Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.

BURST SEQUENCE TABLE

Interleaved Burst Sequence (when LBO# = HIGH or NC)

Operation

A18~A2

A1,A0

First access, latch external address

A18~A2

0 , 0

0 , 1

1 , 0

1 , 1

Second access(first burst address)

latched A18~A2

0 , 1

0 , 0

1 , 1

1 , 0

Third access(second burst address)

latched A18~A2

1 , 0

1 , 1

0 , 0

0 , 1

Fourth access(third burst address)

latched A18~A2

1 , 1

1 , 0

0 , 1

0 , 0

Linear Burst Sequence

Operation

A18~A2

A1,A0

First access, latch external address

A18~A2

0 , 0

0 , 1

1 , 0

1 , 1

Second access(first burst address)

latched A18~A2

0 , 1

1 , 0

1 , 1

0 , 0

Third access(second burst address)

latched A18~A2

1 , 0

1 , 1

0 , 0

0 , 1

Fourth access(third burst address)

latched A18~A2

1 , 1

0 , 0

0 , 1

1 , 0

Note7. The burst sequence wraps around to its initial state upon completion.

TRUTH TABLE

E1#

E2

E3#

ZZ

ADV

W#

BWx#

G#

CKE#

CLK

DQ

Address

used

Operation

H

X

X

L

L

X

X

X

L

L->H

High-Z

None

Deselect Cycle

X

L

X

L

L

X

X

X

L

L->H

High-Z

None

Deselect Cycle

X

X

H

L

L

X

X

X

L

L->H

High-Z

None

Deselect Cycle

X

X

X

L

H

X

X

X

L

L->H

High-Z

None

Continue Deselect Cycle

L

H

L

L

L

H

X

L

L

L->H

Q

External

Read Cycle, Begin Burst

X

X

X

L

H

X

X

L

L

L->H

Q

Next

Read Cycle, Continue Burst

L

H

L

L

L

H

X

H

L

L->H

High-Z

External

NOP/Dummy Read, Begin Burst

X

X

X

L

H

X

X

H

L

L->H

High-Z

Next

Dummy Read, Continue Burst

L

H

L

L

L

L

L

X

L

L->H

D

External

Write Cycle, Begin Burst

X

X

X

L

H

X

L

X

L

L->H

D

Next

Write Cycle, Continue Burst

L

H

L

L

L

L

H

X

L

L->H

High-Z

None

NOP/Write Abort, Begin Burst

X

X

X

L

H

X

H

X

L

L->H

High-Z

Next

Write Abort, Continue Burst

X

X

X

L

X

X

X

X

H

L->H

-

Current

Ignore Clock edge, Stall

X

X

X

H

X

X

X

X

X

X

High-Z

None

Snooze Mode

Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL.

Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more

Synchronous Byte Write Enables are LOW.

Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.