MITSUBISHI LSIs

M5M5T5672TG – 25,22,20

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

4/25

Preliminary

M5M5T5672TG REV.0.1

PIN FUNCTION

Pin

Name

Function

A0~A17

Synchronous

Address

Inputs

These inputs are registered and must meet the setup and hold times around the rising edge of

CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal

burst counter if burst is desired.

BWa#, BWb#,

BWc#, BWd#,

Bwe#, BWf#,

BWg#, BWh#

Synchronous

Byte Write

Enables

These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and

must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be

asserted on the same cycle as the address. BWs are associated with addresses and apply to

subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#

controls DQc, DQPc pins; BWd# controls DQd, DQPd pins; BWe# controls DQe, DQPe pins;

BWf# controls DQf, DQPf pins; BWg# controls DQg, DQPg pins; BWh# controls DQh, DQPh pins.

CLK

Clock Input

This signal registers the address, data, chip enables, byte write enables and burst control inputs

on its rising edge.

All synchronous inputs must meet setup and hold times around the clock's rising edge.

E1#

Synchronous

Chip Enable

This active LOW input is used to enable the device and is sampled only when a new external

address is loaded (ADV is LOW).

E2

Synchronous

Chip Enable

This active HIGH input is used to enable the device and is sampled only when a new external

address is loaded (ADV is LOW). This input can be used for memory depth expansion.

E3#

Synchronous

Chip Enable

This active LOW input is used to enable the device and is sampled only when a new external

address is loaded (ADV is LOW). This input can be used for memory depth expansion.

CKE#

Synchronous

Clock Enable

This active LOW input permits CLK to propagate throughout the device. When HIGH, the device

ignores the CLK input and effectively internally extends the previous CLK cycle. This input must

meet setup and hold times around the rising edge of CLK.

G#

Output Enable

This active LOW asynchronous input enable the data I/O output drivers.

ADV

Synchronous

Address

Advance/Load

When HIGH, this input is used to advance the internal burst counter, controlling burst access after

the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new

address to be loaded at CLK rising edge.

ZZ

Snooze

Enable

This active HIGH asynchronous input causes the device to enter a low-power standby mode in

which all data in the memory array is retained. When active, all other inputs are ignored. When

this pin is LOW or NC, the SRAM normally operates.

W#

Synchronous

Read/Write

This active input determines the cycle type when ADV is LOW. This is the only means for

determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice

versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations

and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs

occur if all byte write enables are LOW.

DQa,DQPa,DQb,DQPb,

DQc,DQPc,DQd,DQPd,

DQe,DQPe,DQf,DQPf,

DQg,DQPg,DQh,DQPh

Synchronous

Data I/O

Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is

DQd,DQPd pins; Byte “e” is DQe, DQPe pins; Byte “f” is DQf, DQPf pins; Byte “g” is DQg, DQPg

pins; Byte “h” is DQh, DQPh pins. Input data must meet setup and hold times around CLK rising

edge.

LBO#

Burst Mode

Control

This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is

HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input

leak current to this pin.

Core Power Supply

Ground

I/O buffer Power supply

TDI

Test Data Input

TDO

Test Data Output

TCK

Test Clock

TMS

Test Mode Select

These pins are used for Boundary Scan Test.

NC

No Connect

These pins are not internally connected and may be connected to ground.