MITSUBISHI LSIs

M5M5Y5636TG – 25,22,20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

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Preliminary

M5M5Y5636TG REV.0.6

BLOCK DIAGRAM

Note3. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.

Note4. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION

and timing diagrams for detailed information.

ADDRESS

REGISTER

19

WRITE ADDRESS

REGISTER1

WRITE ADDRESS

REGISTER2

A1

A0

LINEAR/

INTERLEAVED

BURST

COUNTER

D1

D0

Q1

Q0

A1'

A0'

19

17

WRITE REGISTRY

AND

DATA COHERENCY

CONTROL LOGIC

BYTE a

|

BYTE d

WRITE

DRIVERS

256Kx36

MEMORY

ARRAY

INPUT

REGISTER1

INPUT

REGISTER0

READ

LOGIC

19

19

36

DQa

LBO#

DQPa

DQb

DQPb

DQc

DQPc

DQd

DQPd

A0

A1

A2~18

CLK

E2

E1#

E3

BWa#

BWb#

ADV

W#

EP2

EP3

CQ1

CQ1#

CQ2

CQ2#

BWc#

BWd#

CHIP ENABLE

CONTROL

LOGIC

ZQ