MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

Ver. 1.1

FUNCTION

BLOCK DIAGRAM

The operation mode of the M5M51008D series are determined by

Each mode is summarized in the function table.

A write cycle is executed whenever the low level W overlaps with

before the write cycle and must be stable during the entire cycle.

to these edge to be maintained. The output enable input OE

directly controls the output stage. Setting the OE at a high level,

the output stage is in a high-impedance state, and the data bus

contention problem in the write cycle is eliminated.

A read cycle is executed by setting W at a high level and OE at a

a non-selectable mode in which both reading and writing are

disabled. In this mode, the output stage is in a high- impedance

state, allowing OR-tie with other chips and memory expansion by

data can be held at +2V power supply, enabling battery back-up

operation during power failure or power-down operation in the non-

selected mode.

W

OE

Mode

DQ

L

L

H

H

H

H

L

H

Non selection

Write

Read

High-impedance

Din

Dout

Active

Stand-by

Non selection High-impedance

High-impedance

Active

Active

Stand-by

FUNCTION TABLE

L

H

L

X

H

X

X

X

X

L

X

X

CLOCK

GENERATOR

131072 WORDS

X 8 BITS

(512 ROWS

X128 COLUMNS

X 16BLOCKS)

21

22

23

25

26

27

28

29

13

14

15

17

18

19

20

21

5

30

6

32

8

29

22

30

24

32

16

24

A3

A2

A5

A6

A7

A12

A14

A16

A15

A13

A8

A9

A11

A1

A0

A10

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

W

S1

S2

OE

GND

(0V)

* Pin numbers inside dotted line show those of TSOP

*

*

DATA

INPUTS/

OUTPUTS

WRITE

CONTROL

INPUT

CHIP

SELECT

INPUTS

OUTPUT

ENABLE

INPUT

ADDRESS

INPUTS

A4

2

7

10

3

4

5

6

7

10

9

11

12

13

14

15

18

17

2

31

2

3

4

28

27

26

1

25

20

19

11

12

31

23

16

8

Note 1: "H" and "L" in this table mean VIH and VIL, respectively.

2: "X" in this table should be "H" or "L".