HD6437145 datasheet(11/930 Pages) RENESAS

Part #	HD6437145

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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11 / 930 page

Rev.4.00 Mar. 27, 2008, Page xi of xliv

REJ09B0108-0400

Section 6 Interrupt Controller (INTC) .............................................................. 77

6.1

Features ............................................................................................................................. 77

6.2

Input/Output Pins .............................................................................................................. 79

6.3

Register Descriptions ........................................................................................................ 79

6.3.1

Interrupt Control Register 1 (ICR1) ..................................................................... 80

6.3.2

Interrupt Control Register 2 (ICR2) ..................................................................... 82

6.3.3

IRQ Status Register (ISR).................................................................................... 84

6.3.4

Interrupt Priority Registers A to J (IPRA to IPRJ)............................................... 85

6.4

Interrupt Sources ...............................................................................................................87

6.4.1

External Interrupts ............................................................................................... 87

6.4.2

On-Chip Peripheral Module Interrupts ................................................................ 88

6.4.3

User Break Interrupt ............................................................................................ 88

6.4.4

H-UDI Interrupt ................................................................................................... 89

6.5

Interrupt Exception Processing Vectors Table .................................................................. 90

6.6

Operation........................................................................................................................... 93

6.6.1

Interrupt Sequence ............................................................................................... 93

6.6.2

Stack after Interrupt Exception Processing .......................................................... 95

6.7

Interrupt Response Time ................................................................................................... 96

6.8

Data Transfer with Interrupt Request Signals ................................................................... 98

6.8.1

Handling Interrupt Request Signals as Sources for DTC Activating and

CPU Interrupt, but Not DMAC Activating .......................................................... 99

6.8.2

Handling Interrupt Request Signals as Sources for Activating DMAC,

but Not CPU Interrupt and DTC Activating ........................................................ 99

6.8.3

Handling Interrupt Request Signals as Source for DTC Activating,

but Not CPU Interrupt and DMAC Activating .................................................... 99

6.8.4

Handling Interrupt Request Signals as Source for CPU Interrupt

but Not DMAC and DTC Activating ................................................................... 100

Section 7 User Break Controller (UBC) ........................................................... 101

7.1

Features ............................................................................................................................. 101

7.2

Register Descriptions ........................................................................................................ 103

7.2.1

User Break Address Register (UBAR) ................................................................ 103

7.2.2

User Break Address Mask Register (UBAMR) ................................................... 103

7.2.3

User Break Bus Cycle Register (UBBR) ............................................................. 104

7.2.4

User Break Control Register (UBCR).................................................................. 105

7.3

Operation........................................................................................................................... 106

7.3.1

Flow of User Break Operation ............................................................................. 106

7.3.2

Break on On-Chip Memory Instruction Fetch Cycle ........................................... 108

7.3.3

Program Counter (PC) Values Saved................................................................... 108

7.4

Examples of Use ............................................................................................................... 109

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