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HD6433694G Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD6433694G Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 450 page Rev.5.00 Nov. 02, 2005 Page ix of xxviii Contents Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Internal Block Diagram..........................................................................................................4 1.3 Pin Arrangement .................................................................................................................... 6 1.4 Pin Functions ......................................................................................................................... 9 Section 2 CPU......................................................................................................13 2.1 Address Space and Memory Map ........................................................................................ 14 2.2 Register Configuration......................................................................................................... 17 2.2.1 General Registers .................................................................................................... 18 2.2.2 Program Counter (PC) ............................................................................................ 19 2.2.3 Condition-Code Register (CCR)............................................................................. 19 2.3 Data Formats........................................................................................................................ 21 2.3.1 General Register Data Formats ............................................................................... 21 2.3.2 Memory Data Formats ............................................................................................ 23 2.4 Instruction Set ...................................................................................................................... 24 2.4.1 Table of Instructions Classified by Function .......................................................... 24 2.4.2 Basic Instruction Formats ....................................................................................... 33 2.5 Addressing Modes and Effective Address Calculation ........................................................ 34 2.5.1 Addressing Modes .................................................................................................. 34 2.5.2 Effective Address Calculation ................................................................................ 38 2.6 Basic Bus Cycle ................................................................................................................... 40 2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 40 2.6.2 On-Chip Peripheral Modules .................................................................................. 41 2.7 CPU States ........................................................................................................................... 42 2.8 Usage Notes ......................................................................................................................... 43 2.8.1 Notes on Data Access to Empty Areas ................................................................... 43 2.8.2 EEPMOV Instruction.............................................................................................. 43 2.8.3 Bit Manipulation Instruction................................................................................... 43 Section 3 Exception Handling .............................................................................49 3.1 Exception Sources and Vector Address ............................................................................... 49 3.2 Register Descriptions ...........................................................................................................51 3.2.1 Interrupt Edge Select Register 1 (IEGR1) .............................................................. 51 3.2.2 Interrupt Edge Select Register 2 (IEGR2) .............................................................. 52 3.2.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 53 3.2.4 Interrupt Flag Register 1 (IRR1)............................................................................. 54 |
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