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H8S-2322R Datasheet(PDF) 5 Page - Renesas Technology Corp |
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H8S-2322R Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 1302 page  Rev.6.00 Sep. 27, 2007 Page v of xxx REJ09B0220-0600 Preface This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), a 16-bit timer pulse unit (TPU), a watchdog timer (WDT), a serial communication interface (SCI), DMA controller (DMAC), a D/A converter, an A/D converter, and I/O ports as on-chip supporting modules. This LSI is suitable for use as an embedded processor for high-level control systems. Its on-chip ROM are flash memory (F-ZTAT™*) and mask ROM that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2329 Group, H8S/2328 Group in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2329 Group, H8S/2328 Group to the above audience. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. • In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in appendix B, Internal I/O Registers. Example: Bit order: The MSB is on the left and the LSB is on the right. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. (http://www.renesas.com/eng/) |
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