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H8S2673 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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H8S2673 Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 979 page  Rev. 3.00 Mar 17, 2006 page ix of l Item Page Revision (See Manual for Details) 10.15.4 Pin Functions 515 • PG3/ CS3/RAS3/CAS, PG2/CS2/RAS2/RAS Description amended The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits RMTS2 to RMTS0. 515 • PG1/ CS1, PG0/CS0 Description amended The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, and bit CSnE. 10.16.4 Pin Functions 520 • PH1/ CS5/RAS5/SDRAMφ Description amended The pin function is switched as shown below according to the operating mode, DCTL pin, bit EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR. 11.1 Features Table 11.1 TPU Functions 523 Table 11.1 amended Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture —— 11.3.9 Timer Synchronous Register (TSYR) 558 Bits 7, 6 initial value amended (Before) - → (After) All 0 15.3.9 Bit Rate Generator (BRR) Table 15.2 Relationships between N Setting in BRR and Bit Rate B 679 Table 15.2 amended Mode Bit Rate Error Smart Card Interface Mode B = Error (%) = B × S × 22n+1 × (N + 1) φ × 106 {} – 1 × 100 S × 22n+1 × (N + 1) φ × 106 |
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