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BQ27500DRZT Datasheet(PDF) 6 Page - Texas Instruments |
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BQ27500DRZT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 41 page  3.8 INTEGRATING ADC (COULOMB COUNTER) CHARACTERISTICS 3.9 ADC (TEMPERATURE AND CELL MEASUREMENT) CHARACTERISTICS 3.10 DATA FLASH MEMORY CHARACTERISTICS 3.11 I 2C-COMPATIBLE INTERFACE COMMUNICATION TIMING CHARACTERISTICS bq27500 bq27501 System-Side Impedance Track™ Fuel Gauge SLUS785D – SEPTEMBER 2007 – REVISED APRIL 2008 www.ti.com TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSR Input voltage range (VSR = V(SRN) – V(SRP)) –0.125 0.125 V tSR_CONV Conversion time Single conversion 1 s Resolution 14 15 bits VSR_OS Input offset 10 µV INL Integral nonlinearity error ±0.007 ±0.034 % FSR ZSR_IN Effective input resistance(1) 2.5 M Ω ISR_LKG Input leakage current(1) 0.3 µA (1) Specified by design. Not tested in production. TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VADC_IN Input voltage range –0.2 1 V tADC_CONV Conversion time 125 ms Resolution 14 15 bits VADC_OS Input offset 1 mV Effective input resistance (TS, RID ZADC1 8 M Ω [bq27501 only])(1) bq27500/1 not measuring cell voltage 8 M Ω ZADC2 Effective input resistance (BAT)(1) bq27500/1 measuging cell voltage 100 k Ω IADC_LKG Input leakage current(1) 0.3 µA (1) Specified by design. Not tested in production. TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tON Data retention(1) 10 Years Flash-programming write cycles(1) 20,000 Cycles tWORDPROG Word programming time(1) 2 ms ICCPROG Flash-write supply current(1) 5 10 mA (1) Specified by design. Not production tested TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr SCL/SDA rise time 1 µs tf SCL/SDA fall time 300 ns tw(H) SCL pulse duration (high) 4 µs tw(L) SCL pulse duration (low) 4.7 µs tsu(STA) Setup for repeated start 4.7 µs td(STA) Start to first falling edge of SCL 4 µs tsu(DAT) Data setup time 250 ns ELECTRICAL SPECIFICATIONS 6 Submit Documentation Feedback |
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