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Document Number: 70061

S-71009–Rev. I, 14-May-07

Vishay Siliconix

DG406/407

APPLICATIONS HINTS

Sampling speed is limited by two consecutive events: the

transition time of the multiplexer, and the settling time of the

sampled signal at the output.

source impedance, multiplexer and load capacitances,

charge injection of the multiplexer and accuracy desired.

The settling time for the multiplexer alone can be derived

from the model shown in Figure 5. Assuming a low

impedance signal source like that presented by an op amp or

a buffer amplifier, the settling time of the RC network for a

given accuracy is equal to n

τ:

The maximum sampling frequency of the multiplexer is:

(1)

where N = number of channels to scan

For the DG406 then, at room temp and for 12-bit accuracy,

using the maximum limits:

(2)

or

(3)

From the sampling theorem, to properly recover the original

signal, the sampling frequency should be more than twice

the maximum component frequency of the original signal.

This assumes perfect bandlimiting. In a real application

sampling at three to four times the filter cutoff frequency is a

good practice.

Therefore from equation 2 above:

(4)

From this we can see that the DG406 can be used to sample

16 different signals whose maximum component frequency

can be as high as 173 kHz. If for example, two channels are

used to double sample the same incoming signal then its

cutoff frequency can be doubled.

% ACCURACY

# BITS

N

0.25

8

6

0.012

12

9

0.0017

15

11

Figure 5. Simplified Model of One Multiplexer Channel

f

s

1

Nt

SETTLING

t

TRANS

+

()

----------------------------------------------------------

=

f

s

1

16 9

100

Ω

×

10

-12

F

×

() 300 10

-12

s

×

+

-------------------------------------------------------------------------------------------------------

=

f

c

1

4

---

f

s

×

173 kHz

==