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M30291MCT-XXXHP Datasheet(PDF) 10 Page - Renesas Technology Corp |
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M30291MCT-XXXHP Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 499 page A-3 9. Interrupts ___________________________________________________ 70 9.1 Type of Interrupts............................................................................................................ 70 9.1.1 Software Interrupts ................................................................................................... 71 9.1.2 Hardware Interrupts ................................................................................................. 72 9.2 Interrupts and Interrupt Vector ........................................................................................ 73 9.2.1 Fixed Vector Tables .................................................................................................. 73 9.2.2 Relocatable Vector Tables ........................................................................................ 74 9.3 Interrupt Control.............................................................................................................. 75 9.3.1 I Flag ........................................................................................................................ 78 9.3.2 IR Bit ........................................................................................................................ 78 9.3.3 ILVL2 to ILVL0 Bits and IPL...................................................................................... 78 9.4 Interrupt Sequence ......................................................................................................... 79 9.4.1 Interrupt Response Time .......................................................................................... 80 9.4.2 Variation of IPL when Interrupt Request is Accepted ............................................... 80 9.4.3 Saving Registers ...................................................................................................... 81 9.4.4 Returning from an Interrupt Routine......................................................................... 83 9.5 Interrupt Priority .............................................................................................................. 83 9.5.1 Interrupt Priority Resolution Circuit .......................................................................... 83 ______ 9.6 INT Interrupt ................................................................................................................... 85 ______ 9.7 NMI Interrupt................................................................................................................... 86 9.8 Key Input Interrupt .......................................................................................................... 86 9.9 CAN0 Wake-up Interrupt ................................................................................................ 87 9.10 Address Match Interrupt ............................................................................................... 87 10. Watchdog Timer ____________________________________________ 89 10.1 Count Source Protective Mode..................................................................................... 90 11. DMAC ____________________________________________________ 91 11.1 Transfer Cycles ............................................................................................................ 96 11.1.1 Effect of Source and Destination Addresses ......................................................... 96 11.1.2 Effect of Software Wait .......................................................................................... 96 11.2. DMA Transfer Cycles ................................................................................................... 98 11.3 DMA Enable .................................................................................................................. 99 11.4 DMA Request................................................................................................................99 11.5 Channel Priority and DMA Transfer Timing ................................................................ 100 |
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