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HD64F2148AV Datasheet(PDF) 8 Page - Renesas Technology Corp |
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HD64F2148AV Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 1177 page Rev. 4.00 Sep 27, 2006 page viii of xliv Item Page Revision (See Manual for Details) 14 Mode 1 description of pin 35 amended (Before) P67/TMOX/CIN/ KIN7/IRQ7 → (After) P67/TMOX/CIN7/ KIN7/IRQ7 1.3.2 Pin Functions in Each Operating Mode Table 1.2 (a) Pin Functions in Each Operating Mode 17 Modes 2 and 3 in single chip modes of pin 95 amended (Before) P82 → (After) P82/HIFSD 19 Mode 1 description of pin 35 amended (Before) P67/CIN/ KIN7/IRQ7 → (After) P67/CIN7/KIN7/IRQ7 Table 1.2 (b) H8S/2147N Pin Functions in Each Operating Mode 21 Modes 2 and 3 in single chip modes of pin 95 amended (Before) P82 → (After) P82/HIFSD 1.3.3 Pin Functions Table 1.3 Pin Functions 30 Table 1.3 amended Pin No. Type Symbol FP-100B TFP-100B I/O Name and Function Host interface (HIF) HIRQ11 HIRQ1 HIRQ12 HIRQ3 HIRQ4 52 53 54 91 90 Output Host interrupt 11, 1, 12, 3, and 4: Output pins for interrupt requests to the host. 33 Pin No. Type Symbol FP-100B TFP-100B I/O Name and Function I/O ports PA7 to PA0 10, 11, 20, 21, 30, 31, 47, 48 Input/ output Port A: Eight input/output pins. The data direction of each pin can be selected in the port A data direction register (PADDR). These pins have built-in MOS input pull-ups. These are the VCCB drive pins. [H8S/2148 Group and H8S/2147N only] 2.6.1 Overview Table 2.1 Instruction Classification 52 Instruction in arithmetic operations amended (Before) EG → (After) NEG 3.2.4 Serial Timer Control Register (STCR) 89 Bit 3 bit table amended Bit 3 FLSHE Description 0 Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register and supporting module control register access (Initial value) 1 Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register access (F-ZTAT version only) 4.5 Stack Status after Exception Handling Figure 4.5 (2) Stack Status after Exception Handling (Advanced Mode) 111 Note * deleted from figure 4.5 (2) |
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