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H8S2552 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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H8S2552 Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 982 page  Rev.5.00 Sep. 27, 2007 Page x of xlvi REJ09B0099-0500 2.7.7 Program-Counter Relative ⎯@(d:8, PC) or @(d:16, PC) ...................................... 55 2.7.8 Memory Indirect ⎯@@aa:8 ................................................................................... 55 2.7.9 Effective Address Calculation ................................................................................ 56 2.8 Processing States.................................................................................................................. 59 2.9 Usage Notes ......................................................................................................................... 61 2.9.1 TAS Instruction ...................................................................................................... 61 2.9.2 STM/LDM Instruction............................................................................................ 61 2.9.3 Bit Manipulation Instructions ................................................................................. 61 2.9.4 Access Method for Registers with Write-Only Bits ............................................... 63 Section 3 MCU Operating Modes ......................................................................... 67 3.1 Operating Mode Selection ................................................................................................... 67 3.2 Register Descriptions ...........................................................................................................68 3.2.1 Mode Control Register (MDCR) ............................................................................ 68 3.2.2 System Control Register (SYSCR) ......................................................................... 68 3.3 Operating Mode ................................................................................................................... 70 3.3.1 Mode 6.................................................................................................................... 70 3.3.2 Mode 7.................................................................................................................... 70 3.3.3 Pin Functions .......................................................................................................... 70 3.4 Address Map in Each Operating Mode................................................................................ 72 Section 4 Exception Handling ............................................................................... 75 4.1 Exception Handling Types and Priority............................................................................... 75 4.2 Exception Sources and Exception Vector Table .................................................................. 75 4.3 Reset .................................................................................................................................... 77 4.3.1 Types of Reset ........................................................................................................ 77 4.3.2 Reset Exception Handling ...................................................................................... 78 4.3.3 Interrupts after Reset............................................................................................... 79 4.3.4 State of On-Chip Peripheral Modules after Reset Release ..................................... 79 4.4 Trace Exception Handling ................................................................................................... 79 4.5 Interrupt Exception Handling .............................................................................................. 80 4.6 Trap Instruction Exception Handling................................................................................... 80 4.7 Stack State after Exception Handling .................................................................................. 82 4.8 Usage Note........................................................................................................................... 82 Section 5 Interrupt Controller................................................................................ 85 5.1 Features................................................................................................................................ 85 5.2 Input/Output Pins................................................................................................................. 87 5.3 Register Descriptions ...........................................................................................................87 5.3.1 Interrupt Priority Registers A to M, and O (IPRA to IPRM, IPRO)....................... 88 |
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