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H8S2551 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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H8S2551 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 982 page  Rev.5.00 Sep. 27, 2007 Page xi of xlvi REJ09B0099-0500 5.3.2 IRQ Enable Register (IER) ..................................................................................... 90 5.3.3 IRQ Sense Control Registers H and L (ISCRH and ISCRL) .................................. 91 5.3.4 IRQ Status Register (ISR)....................................................................................... 93 5.4 Interrupt Sources.................................................................................................................. 94 5.4.1 External Interrupts .................................................................................................. 94 5.4.2 Internal Interrupts ................................................................................................... 95 5.4.3 Interrupt Exception Handling Vector Table............................................................ 95 5.5 Operation ........................................................................................................................... 100 5.5.1 Interrupt Control Modes and Interrupt Operation ................................................. 100 5.5.2 Interrupt Control Mode 0 ...................................................................................... 103 5.5.3 Interrupt Control Mode 2 ...................................................................................... 105 5.5.4 Interrupt Exception Handling Sequence ............................................................... 107 5.5.5 Interrupt Response Times ..................................................................................... 109 5.5.6 DTC Activation by Interrupt................................................................................. 110 5.6 Usage Notes ....................................................................................................................... 112 5.6.1 Contention between Interrupt Generation and Disabling...................................... 112 5.6.2 Instructions That Disable Interrupts...................................................................... 113 5.6.3 When Interrupts Are Disabled .............................................................................. 113 5.6.4 Interrupts during Execution of EEPMOV Instruction........................................... 114 5.6.5 IRQ Interrupt ........................................................................................................ 114 5.6.6 NMI Interrupt Usage Notes .................................................................................. 114 Section 6 PC Break Controller (PBC) .................................................................115 6.1 Features.............................................................................................................................. 115 6.2 Register Descriptions ......................................................................................................... 116 6.2.1 Break Address Register A (BARA) ...................................................................... 116 6.2.2 Break Address Register B (BARB) ...................................................................... 117 6.2.3 Break Control Register A (BCRA) ....................................................................... 117 6.2.4 Break Control Register B (BCRB)........................................................................ 118 6.3 Operation ........................................................................................................................... 118 6.3.1 PC Break Interrupt Due to Instruction Fetch ........................................................ 118 6.3.2 PC Break Interrupt Due to Data Access................................................................ 119 6.3.3 Notes on PC Break Interrupt Handling ................................................................. 119 6.3.4 Operation in Transitions to Power-Down Modes ................................................. 119 6.3.5 When Instruction Execution Is Delayed by One State .......................................... 120 6.4 Usage Notes ....................................................................................................................... 121 6.4.1 Module Stop Mode Setting ................................................................................... 121 6.4.2 PC Break Interrupts .............................................................................................. 121 6.4.3 CMFA and CMFB ................................................................................................ 121 6.4.4 PC Break Interrupt when DTC Is Bus Master ...................................................... 121 |
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