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HD6433044 Datasheet(PDF) 8 Page - Renesas Technology Corp |
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HD6433044 Datasheet(HTML) 8 Page - Renesas Technology Corp |
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8 / 905 page  Rev. 7.00 Sep 21, 2005 page viii of xxiv Item Page Revision (See Manual for Details) 19.5.6 Erasing Flowchart and Sample Program Flowchart for Erasing One Block Figure 19.10 Erasing Flowchart 610 Figure amended Enable watchdog timer Wait initial value setting x = 6.25 ms *2 Select erase mode (E bit = 1 in FLMCR) Clear E bit Disable watchdog timer Set top address in block as verify address Select erase-verify mode (EV bit = 1) Wait (tVS1) µs Dummy write to verify address*3 (flash memory latches address) Verify (read memory)*4 Last address? Address + 1 → address Yes OK No No good No No Yes Yes Clear EV bit Clear erase block register (clear bit of erased block to 0) End of block erase Clear EV bit Erase error n ≥ N? n ≥ 5? Erase-verify ends Erasing ends n + 1 Double the erase time (x × 2 → x) → n V E PP Clear bit V E PP Clear bit Wait (x) ms Wait (tVS2) µs Clear erase block register (clear bit of block to be erased to 0) 5. tVS1: 4 µs z: 5 to 10 µs tVS2: 2 µs N: 602 6. The erase time x is successively incremented by the initial set value × 2n–1 (n = 1, 2, 3, 4). An initial value of 6.25 ms or less should be set, and the time for one erasure should be 50 ms or less. *5 *5 *6 |
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