H838704 datasheet(6/402 Pages) RENESAS | 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series

6 page

Rev. 1.00 Dec. 13, 2007 Page vi of xviii

2. Description of Numbers and Symbols

Aspects of the notations for register names, bit names, numbers, and symbolic names in this

manual are explained below.

CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter

input clock. Generation of a

WDTOVF signal or interrupt initializes the TCNT value to 0.

14.3 Operation

The style "register name"_"instance number" is used in cases where there is more than one

instance of the same function or similar functions.

[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.

In descriptions involving the names of bits and bit fields within this manual, the modules and

registers to which the bits belong may be clarified by giving the names in the forms

"module name"."register name"."bit name" or "register name"."bit name".

(1) Overall notation

(2) Register notation

Rev. 0.50, 10/04, page 416 of 914

14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)

14.3.1 Interval Count Operation

(4)

(3)

(2)

Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),

hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.

[Examples] Binary:

B'11 or 11

Hexadecimal: H'EFA0 or 0xEFA0

Decimal:

1234

(3) Number notation

An overbar on the name indicates that a signal or pin is active-low.

[Example]

WDTOVF

Note: The bit names and sentences in the above figure are examples and have nothing to do

with the contents of this manual.

(4) Notation for active-low

When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in

CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in

CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000

and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,

a f/4 clock is selected.

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