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H8-3048B Datasheet(PDF) 11 Page - Renesas Technology Corp |
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H8-3048B Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 901 page  Rev. 3.00 Sep 27, 2006 page xi of xxvi Item Page Revision (See Manual for Details) 13.3.3 Multiprocessor Communication Figure 13.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 495 Figure amended 1 Start bit 0 D0 D1 D7 0/1 Stop bit 1 Data Multi- processor bit Start bit 0 D0 D1 D7 0/1 Stop bit 1 Data 1 Idle (mark) state TDRE TEND TXI request TXI interrupt handler writes data in TDR and clears TDRE flag to 0 1 frame TEI request Multi- processor bit TXI request 13.3.4 Synchronous Operation Clock 500 Description amended An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by setting the C/ A bit in SMR and the CKE1 and CKE0 bits in SCR. See table 13.9. 14.2.3 Serial Mode Register (SMR) Bit 7—GSM Mode (GM) 521 Table amended Bit 7: GM Description 0 Using the regular smart card interface mode • The TEND flag is set 12.5 etu after the beginning of the start bit (Initial value) • Clock output on/off control only 1 Using the GSM mode smart card interface mode • The TEND flag is set 11.0 etu after the beginning of the start bit • Clock output on/off and fixed- (set by SCR) high/fixed-low control 18.5.1 Flash Memory Control Register 1 (FLMCR1) Bit 1—Erase Bit (E) 587 Note amended Note: * Do not access flash memory while the E bit is set to 1. Section 21 Electrical Characteristics Table 21.1 Electrical Characteristics of H8/3048 Group and H8/3048B Group Products 653, 654 Table amended H8/3048B Group Item H8/3048 ZTAT H8/3048 F-ONE (Single Power Supply) H8/3048B Mask ROM V PP pin rating Yes — — Absolute maximum ratings Flash memory charac- teristics* 4 — See table 21.11 — |
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