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M38K01M6 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M38K01M6 Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 328 page Rev.2.00 Oct 05, 2006 page 7 of 13 38K0 Group REJ09B0337-0200 CHAPTER 2 APPLICATION Fig. 2.1.1 Memory map of registers related to I/O port .............................................................. 2 Fig. 2.1.2 Structure of Port Pi (i = 0 to 6) .................................................................................... 3 Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6) ..................................................... 3 Fig. 2.1.4 Structure of Port P0 pull-up control register ............................................................... 4 Fig. 2.1.5 Structure of Port P5 pull-up control register ............................................................... 4 Fig. 2.2.1 Memory map of registers related to interrupt ............................................................. 8 Fig. 2.2.2 Structure of Interrupt request register 1 ...................................................................... 8 Fig. 2.2.3 Structure of Interrupt request register 2 ...................................................................... 9 Fig. 2.2.4 Structure of Interrupt control register 1 ....................................................................... 9 Fig. 2.2.5 Structure of Interrupt control register 2 ..................................................................... 10 Fig. 2.2.6 Structure of Interrupt edge selection register ........................................................... 10 Fig. 2.2.7 Interrupt operation diagram .......................................................................................... 12 Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request ........................................................................................................................................ 13 Fig. 2.2.9 Time up to execution of interrupt processing routine .............................................. 14 Fig. 2.2.10 Timing chart after acceptance of interrupt request .............................................. 14 Fig. 2.2.11 Interrupt control diagram ............................................................................................ 15 Fig. 2.2.12 Example of multiple interrupts ................................................................................... 17 Fig. 2.2.13 Connection example and port P0 block diagram when using key input interrupt . ...................................................................................................................................... 19 Fig. 2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13) . ...................................................................................................................................... 20 Fig. 2.2.15 Sequence of changing relevant register .................................................................. 21 Fig. 2.2.16 Sequence of check of interrupt request bit ............................................................. 22 Fig. 2.3.1 Memory map of registers related to timers ............................................................... 23 Fig. 2.3.2 Structure of Prescaler 12, Prescaler X ...................................................................... 23 Fig. 2.3.3 Structure of Timer 1 ..................................................................................................... 24 Fig. 2.3.4 Structure of Timer 2, Timer X ..................................................................................... 24 Fig. 2.3.5 Structure of Timer X mode register ............................................................................ 25 Fig. 2.3.6 Structure of Interrupt request register 1 .................................................................... 26 Fig. 2.3.7 Structure of Interrupt request register 2 .................................................................... 26 Fig. 2.3.8 Structure of Interrupt control register 1 ..................................................................... 27 Fig. 2.3.9 Structure of Interrupt control register 2 ..................................................................... 27 Fig. 2.3.10 Timers connection and setting of division ratios .................................................... 29 Fig. 2.3.11 Related registers setting ............................................................................................ 29 Fig. 2.3.12 Control procedure ........................................................................................................ 30 Fig. 2.3.13 Peripheral circuit example .......................................................................................... 31 Fig. 2.3.14 Timers connection and setting of division ratios .................................................... 31 Fig. 2.3.15 Related registers setting ............................................................................................ 32 Fig. 2.3.16 Control procedure ........................................................................................................ 32 Fig. 2.3.17 Judgment method of valid/invalid of input pulses .................................................. 33 Fig. 2.3.18 Related registers setting ............................................................................................ 34 Fig. 2.3.19 Control procedure ........................................................................................................ 35 Fig. 2.3.20 Timers connection and setting of division ratios .................................................... 36 Fig. 2.3.21 Related registers setting ............................................................................................ 37 Fig. 2.3.22 Control procedure ........................................................................................................ 38 Fig. 2.4.1 Memory map of registers related to Serial I/O ......................................................... 40 Fig. 2.4.2 Structure of Transmit/Receive buffer register ........................................................... 41 Fig. 2.4.3 Structure of Serial I/O status register ........................................................................ 41 Fig. 2.4.4 Structure of Serial I/O control register ....................................................................... 42 Fig. 2.4.5 Structure of UART control register ............................................................................. 42 List of figures |
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