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HD6437101 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD6437101 Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 486 page  Rev.2.00 Sep. 27, 2007 Page ix of xxxiv REJ09B0394-0200 Item Page Revision (See Manual for Details) 8.7.15 Overflow Flags in Reset Sync PWM Mode Figure 8.81 Reset Sync PWM Mode Overflow Flag 216 Figure amended TGRA_3 (H'FFFF) H'0000 TCFV_3 TCFV_4 TCNT_3 = TCNT_4 Counter cleared by compare match 3A Not set Not set 8.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection 219 Description amended When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. |
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