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SH7050F-ZTAT Datasheet(PDF) 11 Page - Renesas Technology Corp |
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SH7050F-ZTAT Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 841 page Rev. 5.00 Jan 06, 2006 page xi of xx 9.3.10 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 169 9.3.11 Source Address Reload Function ......................................................................... 186 9.3.12 DMA Transfer Ending Conditions....................................................................... 188 9.3.13 DMAC Access from CPU.................................................................................... 189 9.4 Examples of Use ............................................................................................................... 189 9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory .......... 189 9.4.2 Example of DMA Transfer between External RAM and External Device with DACK .......................................................................................................... 190 9.4.3 Example of DMA Transfer between A/D Converter and Internal Memory (Address Reload On)............................................................................................ 190 9.4.4 Example of DMA Transfer between External Memory and SCI1 Send Side (Indirect Address On) .......................................................................................... 192 9.5 Cautions on Use ................................................................................................................ 194 Section 10 Advanced Timer Unit (ATU) ..................................................................... 195 10.1 Overview........................................................................................................................... 195 10.1.1 Features................................................................................................................ 195 10.1.2 Block Diagrams ................................................................................................... 200 10.1.3 Inter-Channel and Inter-Module Signal Connection Diagram ............................. 208 10.1.4 Prescaler Diagram................................................................................................ 209 10.1.5 Pin Configuration................................................................................................. 210 10.1.6 Register and Counter Configuration .................................................................... 212 10.2 Register Descriptions ........................................................................................................ 216 10.2.1 Timer Start Register (TSTR)................................................................................ 216 10.2.2 Timer Mode Register (TMDR) ............................................................................ 218 10.2.3 Prescaler Register 1 (PSCR1) .............................................................................. 220 10.2.4 Timer Control Registers (TCR) ........................................................................... 221 10.2.5 Timer I/O Control Registers (TIOR).................................................................... 225 10.2.6 Trigger Selection Register (TGSR)...................................................................... 233 10.2.7 Timer Status Registers (TSR) .............................................................................. 235 10.2.8 Timer Interrupt Enable Registers (TIER) ............................................................ 252 10.2.9 Interval Interrupt Request Register (ITVRR)....................................................... 264 10.2.10 Down-Count Start Register (DSTR) .................................................................... 267 10.2.11 Timer Connection Register (TCNR).................................................................... 271 10.2.12 Free-Running Counters (TCNT) .......................................................................... 274 10.2.13 Input Capture Registers (ICR) ............................................................................. 276 10.2.14 General Registers (GR)........................................................................................ 277 10.2.15 Down-Counters (DCNT) ..................................................................................... 278 10.2.16 Offset Base Register (OSBR) .............................................................................. 279 10.2.17 Cycle Registers (CYLR) ...................................................................................... 280 10.2.18 Buffer Registers (BFR) ........................................................................................ 281 |
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