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HD6433036VF Datasheet(PDF) 8 Page - Renesas Technology Corp |
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HD6433036VF Datasheet(HTML) 8 Page - Renesas Technology Corp |
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8 / 708 page  Rev.3.00 Mar. 26, 2007 Page viii of xxii REJ09B0353-0300 Item Page Revision (See Manual for Details) 5.3.3 Interrupt Vector Table Table 5.3 Interrupt Sources, Vector Addresses, and Priority 98 Table amended WOVI (interval timer) 5.5.4 Usage Notes Figure 5.9 IRQnF Flag when Interrupt Exception Handling is not Executed 109 Figure amended 1 read 0 written 1 read 0 written Generation condition (2) (Inadvertent clearing) 6.4.2 Precautions on Setting ASTCR and ABWCR * 131 Description amended Modes 5 and 7 ASTCR0 = 0 ABWCR = H'FC 11.2.8 Bit Rate Register (BRR) 349 Description added The baud rate generator is controlled separately for the individual channels, so different values may be set for each. Table 11.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode 351 Table amended φφφφ (MHz) 12 Bit Rate (bits/s) n N Error (%) 300 277 0.16 11.3.4 Synchronous Operation Clock 376 Description amended An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 and CKE0 bits in SCR and the C/ A bit in SMR. See table 11.9. |
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