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7643 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 424 page  Rev.2.00 Aug 28, 2006 page 7 of 12 7643 Group REJ09B0133-0200 Fig. 2.4.1 Memory map of registers related to UART ............................................................... 37 Fig. 2.4.2 Structure of UART mode register ............................................................................... 38 Fig. 2.4.3 Structure of UART control register ............................................................................. 39 Fig. 2.4.4 Structure of UART status register .............................................................................. 40 Fig. 2.4.5 Structure of UART RTS control register .................................................................... 40 Fig. 2.4.6 Structure of UART baud rate generator .................................................................... 41 Fig. 2.4.7 Structure of UART transmit/receive buffer registers 1, 2 ........................................ 42 Fig. 2.4.8 Structure of Interrupt request register A .................................................................... 43 Fig. 2.4.9 Structure of Interrupt request register B .................................................................... 43 Fig. 2.4.10 Structure of Interrupt control register A ................................................................... 44 Fig. 2.4.11 Structure of Interrupt control register B ................................................................... 44 Fig. 2.4.12 UART transfer data format ........................................................................................ 45 Fig. 2.4.13 Connection diagram .................................................................................................... 49 Fig. 2.4.14 Timing chart ................................................................................................................. 49 Fig. 2.4.15 Registers setting for transmitter ................................................................................ 50 Fig. 2.4.16 Registers setting for receiver (1) .............................................................................. 51 Fig. 2.4.17 Registers setting for receiver (2) .............................................................................. 52 Fig. 2.4.18 Control procedure of transmitter ............................................................................... 53 Fig. 2.4.19 Control procedure of receiver .................................................................................... 54 Fig. 2.4.20 Connection diagram .................................................................................................... 56 Fig. 2.4.21 Registers setting related to UART address mode .................................................. 57 Fig. 2.4.22 Control procedure (1) ................................................................................................. 58 Fig. 2.4.23 Control procedure (2) ................................................................................................. 59 Fig. 2.4.24 Connection diagram .................................................................................................... 60 Fig. 2.4.25 Registers setting (1) ................................................................................................... 61 Fig. 2.4.26 Registers setting (2) ................................................................................................... 62 Fig. 2.4.27 Registers setting (3) ................................................................................................... 63 Fig. 2.4.28 Control procedure (1) ................................................................................................. 64 Fig. 2.4.29 Control procedure (2) ................................................................................................. 65 Fig. 2.4.30 Connection diagram .................................................................................................... 66 Fig. 2.4.31 Registers setting (1) ................................................................................................... 67 Fig. 2.4.32 Registers setting (2) ................................................................................................... 68 Fig. 2.4.33 Registers setting (3) ................................................................................................... 69 Fig. 2.4.34 Registers setting (4) ................................................................................................... 70 Fig. 2.4.35 Control procedure (1) ................................................................................................. 71 Fig. 2.4.36 Control procedure (2) ................................................................................................. 72 Fig. 2.5.1 Memory map of registers related to DMAC .............................................................. 75 Fig. 2.5.2 Structure of DMAC index and status register ........................................................... 76 Fig. 2.5.3 Structure of DMAC channel x (x = 0, 1) mode register 1 ...................................... 77 Fig. 2.5.4 Structure of DMAC channel 0 mode register 2 ........................................................ 79 Fig. 2.5.5 Structure of DMAC channel 1 mode register 2 ........................................................ 80 Fig. 2.5.6 Structure of DMAC channel x source registers Low, High ..................................... 81 Fig. 2.5.7 Structure of DMAC channel x destination registers Low, High .............................. 81 Fig. 2.5.8 Structure of DMAC channel x transfer count registers Low, High ......................... 82 Fig. 2.5.9 Structure of Interrupt request register A .................................................................... 83 Fig. 2.5.10 Structure of Interrupt control register A ................................................................... 83 Fig. 2.5.11 Transfer mode overview ............................................................................................. 84 Fig. 2.5.12 Basic operation of registers transferring .................................................................. 85 List of figures |
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