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3820 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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3820 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 349 page  List of figures 3820 GROUP USER’S MANUAL i List of figures CHAPTER 1. HARDWARE Fig. 1 Pin configuration of M38203M4-XXXFP .................................................................................. 1-2 Fig. 2 Pin configuration of M38203M4-XXXGP/HP ........................................................................... 1-3 Fig. 3 Function block diagram ........................................................................................................... 1-4 Fig. 4 Part numbering ........................................................................................................................ 1-7 Fig. 5 Memory expansion plan (1) ..................................................................................................... 1-8 Fig. 6 Memory expansion plan (2) ..................................................................................................... 1-9 Fig. 7 Memory expansion plan (3) ................................................................................................... 1-10 Fig. 8 Structure of CPU mode register ............................................................................................ 1-11 Fig. 9 Memory map diagram ............................................................................................................ 1-12 Fig. 10 Memory map of special function register (SFR) .................................................................. 1-14 Fig. 11 Structure of PULL register A and PULL register B .............................................................. 1-15 Fig. 12 Port block diagram (1) ......................................................................................................... 1-16 Fig. 13 Port block diagram (2) ......................................................................................................... 1-17 Fig. 14 Port block diagram (3) ......................................................................................................... 1-18 Fig. 15 Interrupt control ................................................................................................................... 1-20 Fig. 16 Structure of interrupt-related registers ................................................................................. 1-21 Fig. 17 Connection example when using key input interrupt and port P2 block diagram ................ 1-21 Fig. 18 Timer block diagram ............................................................................................................ 1-22 Fig. 19 Structure of timer X mode register ....................................................................................... 1-23 Fig. 20 Structure of timer Y mode register ....................................................................................... 1-24 Fig. 21 Structure of timer 123 mode register ................................................................................... 1-25 Fig. 22 Block diagram of clock synchronous serial I/O1 .................................................................. 1-26 Fig. 23 Operation of clock synchronous serial I/O1 function ........................................................... 1-26 Fig. 24 Block diagram of UART serial I/O1 ...................................................................................... 1-27 Fig. 25 Operation of UART serial I/O1 function ............................................................................... 1-27 Fig. 26 Structure of serial I/O1 control registers .............................................................................. 1-29 Fig. 27 Structure of serial I/O2 control register ................................................................................ 1-29 Fig. 28 Block diagram of serial I/O2 function ................................................................................... 1-30 Fig. 29 Timing of serial I/O2 function ............................................................................................... 1-31 Fig. 30 Structure of segment output enable register and LCD mode register ................................. 1-32 Fig. 31 Block diagram of LCD controller/driver ................................................................................ 1-33 Fig. 32 Example of circuit at each bias ............................................................................................ 1-34 Fig. 33 LCD display RAM map ........................................................................................................ 1-35 Fig. 34 LCD drive waveform (1/2 bias) ............................................................................................ 1-36 Fig. 35 LCD drive waveform (1/3 bias) ............................................................................................ 1-37 Fig. 36 Watchdog timer block diagram ............................................................................................ 1-38 Fig. 37 Structure of watchdog timer control register ........................................................................ 1-38 Fig. 38 Structure of φ output control register ...................................................................................1-39 Fig. 39 Example of reset circuit ....................................................................................................... 1-40 Fig. 40 Internal state of microcomputer immediately after reset ...................................................... 1-40 Fig. 41 Reset sequence ................................................................................................................... 1-41 Fig. 42 Ceramic resonator circuit ..................................................................................................... 1-42 Fig. 43 External clock input circuit ................................................................................................... 1-42 Fig. 44 Clock generating circuit block diagram ................................................................................ 1-43 Fig. 45 State transitions of internal clock φ ............................................................................................... 1-44 Fig. 46 Programming and testing of One Time PROM version ....................................................... 1-46 Fig. 47 Circuit for measuring output switching characteristics ........................................................ 1-64 Fig. 48 Timing diagram .................................................................................................................... 1-65 Fig. 49 ICC–VCC characteristic example (f(XIN = 8 MHz)) ................................................................ 1-66 Fig. 50 ICC–VCC characteristic example (f(XIN = 4 MHz)) ................................................................ 1-66 Fig. 51 ICC–VCC characteristic example (f(XIN) = 32 kHz, oscillator used) ...................................... 1-67 Fig. 52 ICC–f(XIN) characteristic example (VCC = 3.0 V) .................................................................. 1-68 |
Similar Part No. - 3820_03 |
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Similar Description - 3820_03 |
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