HD64F7058BP80K datasheet(7/1130 Pages) RENESAS

Part #	HD64F7058BP80K

Description	Renesas SuperHTM RISC engine

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Manufacturer	RENESAS [Renesas Technology Corp]

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7 / 1130 page

Rev. 3.0, 09/04, page iv of xxxviii

Item

Page

Revisions (See Manual for Details)

7.5 Interrupt Response Time

Table 7.5 Interrupt Response Time

122

Table amended

Item

Peripheral

Module

NMI

Number of States

IRQ

Notes

Synchronizing input signal

(synchronized with

peripheral clock P

φ) with

internal clock

φ and DMAC

activation judgment

0 or 6

[0 or 3]

1 to 4

[1 or 2]

6 to 9

[3 to 5]

Interrupt

response time

(7 or 13) +

m1 + m2 +

m3 + X

Total:

(8 to 11) +

m1 + m2 +

m3 + X

(13 to 16) +

m1 + m2 +

m3 + X

17 + 2 (m1 +

m2 + m3) +

m4

Maximum:

15 + 2 (m1 +

m2 + m3) +

m4

20 + 2 (m1 +

m2 + m3) +

m4

10

Minimum:

11

16

For the number of states

required for each interrupt,

see the note (*) below.

The values enclosed in [ ]

are values for when the

multiplication ratio is 4.

Wait for completion of

sequence currently

being executed by CPU

X (

≥ 0)

The longest sequence is for

interrupt or address-error

exception processing (X = 4

+ m1 + m2 + m3 + m4). If an

interrupt-masking instruction

follows, however, the time

may be even longer.

Time from start of interrupt

exception processing until

fetch of first instruction of

exception service routine

starts

Note: * Number of states needed for synchronization and DMAC activation judgment

The relations between numbers of states needed for synchronizing an input signal

(synchronized with the peripheral clock P

φ) with the internal clock φ and DMAC activation

judgment and vector numbers are shown below.

0 state: 9, 10, 12, 13, 14, 72, 74, 76, 78, 189, 193, and 224

6 states: Peripheral module interrupts other than the above. However, vector number

222 (HCAN0/RM0) is different from the others.

For an interrupt with vector number 222 (HCAN0/RM0), the needed states differ from

other interrupts since the interrupt by HCAN0 mailbox 0 can activate the DMAC.

HCAN0 mailbox 0: 7 states

Other than above: 6 states

The same number of states is needed to cancel interrupt sources.

If the necessary number of states is not secured after flag clear of the interrupt

source, the interrupt may occur again.

5 + m1 + m2 + m3

Performs the PC and SR

saves and vector address

fetch.

Compare identified interrupt

priority with SR mask level

22

2

7.5 Interrupt Response Time

Figure 7.4 Example of Pipeline

Operation when an IRQ Interrupt is

Accepted

123

Figure amended

Interrupt acceptance

Instruction

Interrupt controller

processing

Synchronization

of

IRQ

2

6 to 9

3

m1 m2

1 m3 1

FD

E

M

E

M

E

F

FD

E

5 + m1 + m2 + m3

Overrun fetch

Interrupt service routine

start instruction

9.1.5 Address Map

Table 9.3 Address Map

• Number of Access Cycles for On-Chip

Peripheral Module Registers

146

Newly added

10.3.2 DMA Transfer Requests

179

Description added

In on-chip peripheral module request mode, when the

DMAC accepts the transfer request, the next transfer

request is ignored until a single transfer ends in cycle

steal mode or all transfers end in burst mode. Only

when the address reload function is used, the next

transfer request is accepted after the fourth transfer.

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