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R5F72867D100FA Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R5F72867D100FA Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 1726 page Rev. 1.00 Jun. 26, 2008 Page xi of xxx 5.3 Address Errors ..................................................................................................................105 5.3.1 Address Error Sources ...................................................................................... 105 5.3.2 Address Error Exception Handling ................................................................... 106 5.4 Register Bank Errors......................................................................................................... 107 5.4.1 Register Bank Error Sources............................................................................. 107 5.4.2 Register Bank Error Exception Handling ......................................................... 107 5.5 Interrupts........................................................................................................................... 108 5.5.1 Interrupt Sources............................................................................................... 108 5.5.2 Interrupt Priority Level ..................................................................................... 109 5.5.3 Interrupt Exception Handling ........................................................................... 110 5.6 Exceptions Triggered by Instructions ............................................................................... 111 5.6.1 Types of Exceptions Triggered by Instructions ................................................ 111 5.6.2 Trap Instructions ............................................................................................... 112 5.6.3 Slot Illegal Instructions ..................................................................................... 112 5.6.4 General Illegal Instructions............................................................................... 113 5.6.5 Integer Division Instructions............................................................................. 113 5.7 When Exception Sources Are Not Accepted .................................................................... 114 5.8 Stack Status after Exception Handling Ends..................................................................... 115 5.9 Usage Notes ...................................................................................................................... 117 5.9.1 Value of Stack Pointer (SP) .............................................................................. 117 5.9.2 Value of Vector Base Register (VBR) .............................................................. 117 5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 117 Section 6 Interrupt Controller (INTC) .................................................................119 6.1 Features............................................................................................................................. 119 6.2 Input/Output Pins.............................................................................................................. 121 6.3 Register Descriptions ........................................................................................................ 122 6.3.1 Interrupt Priority Registers 01, 02, 05 to 18 (IPR01, IPR02, IPR05 to IPR18) ...................................................................... 123 6.3.2 Interrupt Control Register 0 (ICR0).................................................................. 125 6.3.3 Interrupt Control Register 1 (ICR1).................................................................. 126 6.3.4 IRQ Interrupt Request Register (IRQRR)......................................................... 127 6.3.5 Bank Control Register (IBCR).......................................................................... 129 6.3.6 Bank Number Register (IBNR)......................................................................... 130 6.3.7 USB-DTC Transfer Interrupt Request Register (USDTENDRR) .................... 132 6.4 Interrupt Sources...............................................................................................................133 6.4.1 NMI Interrupt.................................................................................................... 133 6.4.2 User Break Interrupt ......................................................................................... 133 6.4.3 H-UDI Interrupt ................................................................................................ 133 6.4.4 IRQ Interrupts ................................................................................................... 134 |
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