SH7763 datasheet(11/2026 Pages) RENESAS

Part #	SH7763

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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11 / 2026 page

Rev. 1.00 Oct. 01, 2007 Page xi of lxvi

6.5.4

Data TLB Multiple Hit Exception ........................................................................ 169

6.5.5

Data TLB Miss Exception .................................................................................... 169

6.5.6

Data TLB Protection Violation Exception............................................................ 170

6.5.7

Initial Page Write Exception ................................................................................. 171

6.6

Memory-Mapped TLB Configuration................................................................................ 172

6.6.1

ITLB Address Array ............................................................................................. 173

6.6.2

ITLB Data Array................................................................................................... 174

6.6.3

UTLB Address Array............................................................................................ 175

6.6.4

UTLB Data Array ................................................................................................. 176

6.7

32-Bit Address Extended Mode ......................................................................................... 177

6.7.1

Overview of 32-Bit Address Extended Mode ....................................................... 178

6.7.2

Transition to 32-Bit Address Extended Mode ...................................................... 178

6.7.3

Privileged Space Mapping Buffer (PMB) Configuration ..................................... 179

6.7.4

PMB Function....................................................................................................... 181

6.7.5

Memory-Mapped PMB Configuration.................................................................. 182

6.7.6

Notes on Using 32-Bit Address Extended Mode .................................................. 184

6.8

Usage Notes ....................................................................................................................... 186

Section 7 Caches ................................................................................................187

7.1

Features.............................................................................................................................. 187

7.2

Register Descriptions ......................................................................................................... 190

7.2.1

Cache Control Register (CCR) ............................................................................. 191

7.2.2

Queue Address Control Register 0 (QACR0) ....................................................... 193

7.2.3

Queue Address Control Register 1 (QACR1) ....................................................... 194

7.2.4

On-Chip Memory Control Register (RAMCR) .................................................... 195

7.3

Operand Cache Operation.................................................................................................. 197

7.3.1

Read Operation ..................................................................................................... 197

7.3.2

Prefetch Operation ................................................................................................ 198

7.3.3

Write Operation .................................................................................................... 199

7.3.4

Write-Back Buffer ................................................................................................ 201

7.3.5

Write-Through Buffer........................................................................................... 201

7.3.6

OC Two-Way Mode ............................................................................................. 201

7.4

Instruction Cache Operation .............................................................................................. 202

7.4.1

Read Operation ..................................................................................................... 202

7.4.2

Prefetch Operation ................................................................................................ 203

7.4.3

IC Two-Way Mode............................................................................................... 203

7.5

Cache Operation Instruction .............................................................................................. 204

7.5.1

Coherency between Cache and External Memory ................................................ 204

7.5.2

Prefetch Operation ................................................................................................ 205

7.6

Memory-Mapped Cache Configuration ............................................................................. 206

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