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3850 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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3850 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 261 page  ii 3850/3851 Group User’s Manual List of figures CHAPTER 2 APPLICATION Fig. 2.1.1 Memory map of registers relevant to I/O port ......................................................... 2-2 Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4) ...................................................................... 2-2 Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) ....................................... 2-3 Fig. 2.2.1 Memory map of registers relevant to timers ............................................................ 2-6 Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y .............................................. 2-6 Fig. 2.2.3 Structure of Timer 1 .................................................................................................... 2-7 Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y ................................................................... 2-7 Fig. 2.2.5 Structure of Timer XY mode register ........................................................................ 2-8 Fig. 2.2.6 Structure of Timer count source set register ........................................................... 2-9 Fig. 2.2.7 Structure of Interrupt request register 1 ................................................................. 2-10 Fig. 2.2.8 Structure of Interrupt request register 2 ................................................................. 2-10 Fig. 2.2.9 Structure of Interrupt control register 1 .................................................................. 2-11 Fig. 2.2.10 Structure of Interrupt control register 2 ................................................................ 2-11 Fig. 2.2.11 Timers connection and setting of division ratios ................................................. 2-13 Fig. 2.2.12 Relevant registers setting ....................................................................................... 2-14 Fig. 2.2.13 Control procedure ..................................................................................................... 2-15 Fig. 2.2.14 Peripheral circuit example ....................................................................................... 2-16 Fig. 2.2.15 Timers connection and setting of division ratios ................................................. 2-16 Fig. 2.2.16 Relevant registers setting ....................................................................................... 2-17 Fig. 2.2.17 Control procedure ..................................................................................................... 2-18 Fig 2.2.18 Judgment method of valid/invalid of input pulses ................................................ 2-19 Fig. 2.2.19 Relevant registers setting ....................................................................................... 2-20 Fig. 2.2.20 Control procedure ..................................................................................................... 2-21 Fig. 2.2.21 Timers connection and setting of division ratios ................................................. 2-22 Fig. 2.2.22 Relevant registers setting ....................................................................................... 2-23 Fig. 2.2.23 Control procedure ..................................................................................................... 2-24 Fig. 2.3.1 Memory map of registers relevant to serial I/O ..................................................... 2-26 Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-27 Fig. 2.3.3 Structure of Serial I/O status register ..................................................................... 2-27 Fig. 2.3.4 Structure of Serial I/O control register .................................................................... 2-28 Fig. 2.3.5 Structure of UART control register .......................................................................... 2-28 Fig. 2.3.6 Structure of Baud rate generator ............................................................................. 2-29 Fig. 2.3.7 Structure of Interrupt edge selection register ........................................................ 2-29 Fig. 2.3.8 Structure of Interrupt request register 2 ................................................................. 2-29 Fig. 2.3.9 Structure of Interrupt control register 2 .................................................................. 2-30 Fig. 48 External clock input circuit ............................................................................................ 1-42 Fig. 49 Structure of MISRG ........................................................................................................ 1-43 Fig. 50 System clock generating circuit block diagram (Single-chip mode) ........................ 1-43 Fig. 51 State transitions of system clock ................................................................................. 1-44 Fig. 52 Programming and testing of One Time PROM version ............................................ 1-46 Fig. 53 Timing chart after an interrupt occurs ......................................................................... 1-48 Fig. 54 Time up to execution of the interrupt processing routine ........................................ 1-48 Fig. 55 A-D conversion equivalent circuit ................................................................................. 1-50 Fig. 56 A-D conversion timing chart.......................................................................................... 1-50 Fig. 57 Structure of MISRG ........................................................................................................ 1-52 Fig. 58 Structure of I2C START/STOP condition control register ......................................... 1-52 Fig. 59 Memory expansion plan of 3850 group ....................................................................... 1-53 Fig. 60 Structure of Interrupt request register 1 of 3850 group ........................................... 1-54 Fig. 61 Structure of Interrupt control register 1 of 3850 group ............................................ 1-54 |
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