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HD6433212F16 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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HD6433212F16 Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 520 page  8.2.3 PWM Output Enable Registers A and B (PWOERA and PWOERB)................ 162 8.2.4 Port 1 Data Direction Register (P1DDR)............................................................ 163 8.2.5 Port 2 Data Direction Register (P2DDR)............................................................ 163 8.2.6 Port 1 Data Register (P1DR) ............................................................................... 163 8.2.7 Port 2 Data Register (P2DR) ............................................................................... 164 8.2.8 Serial/Timer Control Register (STCR)................................................................ 164 8.3 Operation .......................................................................................................................... 166 8.3.1 Correspondence between PWM Data Register Contents and Output Waveform................................................................................................ 166 Section 9 16-Bit Free-Running Timer .......................................................................... 169 9.1 Overview .......................................................................................................................... 169 9.1.1 Features ............................................................................................................... 169 9.1.2 Block Diagram .................................................................................................... 170 9.1.3 Input and Output Pins.......................................................................................... 171 9.1.4 Register Configuration ........................................................................................ 171 9.2 Register Descriptions........................................................................................................ 172 9.2.1 Free-Running Counter (FRC)—H'FF92.............................................................. 172 9.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94 and H'FF96................................................................................................................. 172 9.2.3 Input Capture Register (ICR)—H'FF98 .............................................................. 173 9.2.4 Timer Control Register (TCR)—H'FF90 ............................................................ 174 9.2.5 Timer Control/Status Register (TCSR)—H'FF91 ............................................... 176 9.3 CPU Interface ................................................................................................................... 179 9.4 Operation .......................................................................................................................... 182 9.4.1 FRC Incrementation Timing ............................................................................... 182 9.4.2 Output Compare Timing ..................................................................................... 184 9.4.3 FRC Clear Timing ............................................................................................... 184 9.4.4 Input Capture Timing.......................................................................................... 185 9.4.5 Timing of Input Capture Flag (ICF) Setting ....................................................... 186 9.4.6 Setting of FRC Overflow Flag (OVF) ................................................................ 186 9.5 Interrupts .......................................................................................................................... 187 9.6 Sample Application .......................................................................................................... 187 9.7 Application Notes ............................................................................................................. 188 Section 10 8-Bit Timers .................................................................................................... 193 10.1 Overview .......................................................................................................................... 193 10.1.1 Features ............................................................................................................... 193 10.1.2 Block Diagram .................................................................................................... 194 10.1.3 Input and Output Pins.......................................................................................... 195 10.1.4 Register Configuration ........................................................................................ 196 |
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