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M37481E8-XXXFP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M37481E8-XXXFP Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 337 page  List of Figures i 7480 Group and 7481 Group User’s Manual List of Figures CHAPTER 1 HARDWARE Figure 1.2.1 ROM/RAM Expansion Plan of 7480 Group and 7481 Group (As of September 1997) ............. 1-4 Figure 1.4.1 Pinout of 7480 Group (top view) ........................................................................... 1-8 Figure 1.4.2 Pinout of 7481 Group (top view) ........................................................................... 1-9 Figure 1.6.1 M37480Mx/E8-XXXSP/FP and M37480MxT/E8T-XXXSP/FP Functional Block Diagram ......... 1-12 Figure 1.6.2 M37481Mx/E8-XXXSP, M37481MxT/E8T-XXXSP and M37481E8SS Functional Block Diagram .. 1-13 Figure 1.6.3 M37481Mx/E8-XXXFP, M37481MxT/E8T-XXXFP Functional Block Diagram ............................... 1-14 Figure 1.7.1 CPU Internal Registers ......................................................................................... 1-15 Figure 1.7.2 Operation for Pushing onto and Pulling from Stack ......................................... 1-17 Figure 1.8.1 Access Area ........................................................................................................... 1-20 Figure 1.9.1 Memory Maps of 7480 Group and 7481 Group ................................................ 1-23 Figure 1.9.2 Memory Map of SFR Area ................................................................................... 1-24 Figure 1.9.3 Memory Map of Interrupt Vector Area ................................................................ 1-25 Figure 1.10.1 Block Diagrams of Port Pins P0i and P10–P13 .......................................................... 1-27 Figure 1.10.2 Block Diagram of Port Pins P14–P17 ............................................................................... 1-28 Figure 1.10.3 Block Diagrams of Port Pins P2i to P5i .......................................................................... 1-29 Figure 1.10.4 Memory Map of Registers Associated with I/O Pins ...................................... 1-30 Figure 1.10.5 Port Pi Registers (i = 0 to 5) ............................................................................ 1-31 Figure 1.10.6 Port Pi Direction Registers (i = 0, 1, 4, 5) ...................................................... 1-32 Figure 1.10.7 Port P0 Pull-up Control Register ....................................................................... 1-33 Figure 1.10.8 Port P1 Pull-up Control Register ....................................................................... 1-33 Figure 1.10.9 Port P4P5 Input Control Register ..................................................................... 1-34 Figure 1.10.10 Write and Read of I/O Port Pin ...................................................................... 1-35 Figure 1.10.11 Port P4 and P5 Circuit ..................................................................................... 1-37 Figure 1.11.1 Block Diagram of Interrupt Inputs and Key-On Wakeup Circuit ................... 1-42 Figure 1.11.2 Memory Map of Registers Associated with Interrupt Control ........................ 1-43 Figure 1.11.3 Edge Polarity Selection Register ....................................................................... 1-44 Figure 1.11.4 Interrupt Request Register 1 ............................................................................. 1-45 Figure 1.11.5 Interrupt Request Register 2 ............................................................................. 1-45 Figure 1.11.6 Interrupt Control Register 1 ............................................................................... 1-46 Figure 1.11.7 Interrupt Control Register 2 ............................................................................... 1-46 Figure 1.11.8 Operation When Interrupt Request is Accepted .............................................. 1-50 Figure 1.11.9 Processing Time from Interrupt Generation until Execution of Interrupt Service Routine .... 1-51 Figure 1.11.10 Timing at Interrupt Acceptance ....................................................................... 1-51 Figure 1.11.11 Interrupt Control Diagram ................................................................................. 1-53 Figure 1.11.12 Setting of Interrupts (1) .................................................................................... 1-54 Figure 1.11.13 Setting of Interrupts (2) .................................................................................... 1-55 |
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