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TAS3218IPZP Datasheet(PDF) 7 Page - Texas Instruments |
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TAS3218IPZP Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 79 page  SAP IN Audio processing Control I 2 C 8051 A - MUX 10 :1 2CH ADC 10 chstereo Analog Inputs DAC Mod 6CH DAC SPDIF HPAMP SDIN 1 SDIN 2 SDIN 3 HPOUTL / R SAP OUT SDOUT 1 SCL1 SDA1 SCL 2 SDA2 GPIO 1-4 CS SPDIFOUT / SDOUT 2 3:1 MUX SPDIFIN MUTEZ 2 2 DACOUT 1L/ R 2 DACOUT 2L/ R 2 2 MCLKIN SCLKIN LRCLKIN MCLKOUT SCLKOUT LRCLKOUT 2 A- MUX 11:1 SCLKI LRCLKI LINEOUT 1L/R 2 10 chstereo Clock Control OSC 512Fs AVSS TBD TBD 512 Fs 10pf 10pf AVSS External ASRC MCLKO SCLKO LRCLKO SDO 1 SDO 2 SDO 3 SDIN1A SDIN2B SDIN3B SDIN4B SCLKA LRCLKA MCLKA SCLKB LRCLKB MCLKB MUX MCLKI SCLKI LRCLKI MUX SDI1 SDI2 SDI3 Clocks TAS3218 www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008 Figure 2. Interface to External ASRC The TAS3218 can be configured as either the clock master or clock slave depending on the settings in the clock configuration register. By default, the TAS3218 is configured as the clock master. Figure 3 shows the block diagram of the TAS3218 clocks Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TAS3218 |
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