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TPS51200DRCRG4 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS51200DRCRG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 35 page www.ti.com APPLICATION INFORMATION VIN CAPACITOR VLDO INPUT CAPACITOR OUTPUT CAPACITOR Low VIN Applications S3 and Pseudo-S5 Support Tracking Startup and Shutdown TPS51200 SLUS812 – FEBRUARY 2008 Add a ceramic capacitor, with a value between 1.0- µF and 4.7-µF, placed close to the VIN pin, to stabilize the bias supply (2.5- V rail or 3.3- V rail) from any parasitic impedance from the supply. Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10- µF (or greater) ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at VO. In general, use one-half of the COUT value for input. For stable operation, the total capacitance of the VO output terminal must be greater than 20 µF. Attach three, 10- µF ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series inductance (ESL). If the ESR is greater than 2 m Ω, insert an R-C filter between the output and the VOSNS input to achieve loop stability. The R-C filter time constant should be almost the same as or slightly lower than the time constant of the output capacitor and its ESR. TPS51200 can be used in an application system where either a 2.5-V rail or a 3.3-V rail is available. If only a 5-V rail is available, TPS51100 can be used instead. The TPS51200 minimum input voltage requirement is 2.375 V. If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between –5% and 5% accuracy, or better. The TPS51200 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in the end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VO is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low and the REFIN voltage is less than 0.390 V, TPS51200 enters pseudo-S5 state. Both VO and REFOUT outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4/S5 state). Figure 1 shows a typical startup and shutdown timing diagram for an application that uses S3 and pseudo-S5 support. The TPS51200 also supports tracking startup and shutdown when EN is tied directly to the system bus and not used to turn on or turn off the device. During tracking startup, VO follows REFOUT once REFIN voltage is greater than 0.39 V. REFIN follows the rise of VDDQ rail via a voltage divider. The typical soft-start time for the VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The SS time of the VO output no longer depends on the OCL setting, but it is a function of the SS time of the VDDQ rail. PGOOD is asserted 2 ms after VO is within ±20% of REFOUT. During tracking shutdown, VO falls following REFOUT until REFOUT reaches 0.37 V. Once REFOUT falls below 0.37 V, the internal discharge MOSFETs are turned on and quickly discharge both REFOUT and VO to GND. PGOOD is deasserted once VO is beyond the ±20% range of REFOUT. Figure 2 shows the typical timing diagram for an application that uses tracking startup and shutdown. Copyright © 2008, Texas Instruments Incorporated 9 Product Folder Link(s): TPS51200 |
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